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6090D–DRMSD–12-Feb-07

ATSAM3308B

2.

DSP Array Block Diagram

Figure 2-1.

ATSAM3308B DSP Array Block Diagram

3.

Functional Description

3.1

DSP Array

The ATSAM3308B includes eight on-chip DSPs.

Each DSP (P24) is built around a 2k x 24 RAM and a 1k x 24 ROM. The RAM contains both data

and P24 instructions, the ROM contains typical coefficients such as FFT cosines and windowing.

A P24 sends and receives audio samples through the Sync Bus. It can request external data

such as compressed audio through the Async Bus. Each P24 RAM can be accessed through

the Async Bus.

Each P24 is capable of typical MAC operation loops, including auto-indexing, bit reverse and

butterfly (multiplication of complex numbers). It also includes specialized audio instructions such

as state variable IIR filtering, envelope generation, linear interpolation and wavetable loop.

One P24 is sufficient for processing one channel of MP3 data pump, implementing a multi-tap

delay line or a multi-tap transversal filter. A single P24 is also capable of generating twelve

voices of wavetable sound at 32 kHz sampling rate (8 voices at 48 kHz), including sample

cache, pitch control, 2nd order filter and two envelope generators.

ATSAM3308B

Sync Bus

Async Bus

Audio I/0

External I/O

I/Os,

Timers,

UARTs,

DataFlash,

Ports

Router

Final ACC

MIX

Audio OUT

Audio IN

16 bit Processor

(P16)

Embedded ROM

1k x 16

BIOS and Debug

MMU

External

RAM

ROM

Flash

Embedded RAM

16k x 24

DSP Array (8 P24 DSPs)