CMS6416LAH datasheet(37/46 Pages) FIDELIX

37 / 46 page

Rev1.3, Nov. 2005

CMS6416LAx-15Ex

CLOCK SUSPEND

The clock suspend mode occurs when a column access/

burst is in progress and CKE is registered LOW. In the clock

suspend mode, the internal clock is deactivated, “freezing”

the synchronous logic. For each positive clock edge on which

CKE is sampled LOW, the next internal positive clock edge is

suspended. Any command or data present on the input pins

at the time of a suspended internal clock edge is ignored; any

data present on the DQ pins remains driven; and burst-

counters are not incremented, as long as the clock is sus-

pended. (See examples in Figure 23. and Figure 24. .) Clock

suspend mode is exited by registering CKE HIGH; the internal

clock and related operation will resume on the subsequent

positive clock edge.

BURST READ/SINGLE WRITE

In this mode, all WRITE commands result in the access of a

single column location (burst of one), regardless of the progra-

mmed burst length. The burst read/single write mode is entered

by programming the write burst mode bit (M9) in the mode

according to the programmed burst length and sequence.

Figure 22. Power Down

Input buffers gated off

CLK

Command

NOP

Active

CKE

>=tCKS

NOP

tCKS

All banks Idle

Enter Power Down Mode

Exit Power Down Mode

tRCD

tRAS

tRC

CMS6416LAH Datasheet(PDF) 37 Page - FIDELIX