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AT90USB646 Datasheet(PDF) 202 Page - ATMEL Corporation |
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AT90USB646 Datasheet(HTML) 202 Page - ATMEL Corporation |
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202 / 459 page ![]() 202 7593H–AVR–11/08 ATmega32U6/AT90USB64/128 • Bit 3 – USBSn: Stop Bit Select This bit selects the number of stop bits to be inserted by the Transmitter. The Receiver ignores this setting. • Bit 2:1 – UCSZn1:0: Character Size The UCSZn1:0 bits combined with the UCSZn2 bit in UCSRnB sets the number of data bits (Character SiZe) in a frame the Receiver and Transmitter use. • Bit 0 – UCPOLn: Clock Polarity This bit is used for synchronous mode only. Write this bit to zero when asynchronous mode is used. The UCPOLn bit sets the relationship between data output change and data input sample, and the synchronous clock (XCKn). 18.9.5 USART Baud Rate Registers – UBRRLn and UBRRHn • Bit 15:12 – Reserved Bits Table 18-6. USBS Bit Settings USBSn Stop Bit(s) 01-bit 12-bit Table 18-7. UCSZn Bits Settings UCSZn2 UCSZn1 UCSZn0 Character Size 000 5-bit 001 6-bit 010 7-bit 011 8-bit 100 Reserved 101 Reserved 110 Reserved 111 9-bit Table 18-8. UCPOLn Bit Settings UCPOLn Transmitted Data Changed (Output of TxDn Pin) Received Data Sampled (Input on RxDn Pin) 0 Rising XCKn Edge Falling XCKn Edge 1 Falling XCKn Edge Rising XCKn Edge Bit 15 14131211 10 9 8 – – – – UBRR[11:8] UBRRHn UBRR[7:0] UBRRLn 765 43 210 Read/Write R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 000 00 000 000 00 000 |
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