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AT90USB646 Datasheet(PDF) 49 Page - ATMEL Corporation |
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AT90USB646 Datasheet(HTML) 49 Page - ATMEL Corporation |
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49 / 459 page ![]() 49 7593H–AVR–11/08 ATmega32U6/AT90USB64/128 Figure 6-4. PLL Clocking System 6.10.2 PLL Control and Status Register – PLLCSR • Bit 7..5 – Res: Reserved Bits These bits are reserved bits in the ATmega32U6/AT90USB64/128 and always read as zero. • Bit 4..2 – PLLP2:0 PLL Prescaler These bits allow to configure the PLL input prescaler to generate the 2MHz input clock for the PLL. Note: 1. For AT90USB128x only. Do not use with AT90USB64x. 2. For AT90USB64x and ATmega32U6 only. Do not use with AT90USB128x. 8 MHz RC OSCILLATOR XTAL1 XTAL2 OSCILLATORS PLL 24x PLLE Lock Detector PLOCK clkUSB System Clock clk 2MHz PLL clock Prescaler (48MHz) Bit 7 65 432 1 0 $29 ($29) PLLP2 PLLP1 PLLP0 PLLE PLOCK PLLCSR Read/Write R R R R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0/1 0 Table 6-11. PLL input prescaler configurations PLLP2 PLLP1 PLLP0 Clock Division Factor External XTAL required for USB operation (MHz) 0 0 0 Reserved - 0 0 1 Reserved - 0 1 0 Reserved - 01 1 4 8 1 0 0 Reserved - 10 1 8 (1) 16 (1) 11 0 8 (2) 16 (2) 1 1 1 Reserved - |
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