AT90USB646 datasheet(246/459 Pages) ATMEL

246 / 459 page

246

7593H–AVR–11/08

ATmega32U6/AT90USB64/128

21. USB controller

21.1

Features

• Support full-speed and low-speed.

• Support ping-pong mode (dual bank)

• 832 bytes of DPRAM :

– 1 endpoint 64 bytes max (default control endpoint),

– 1 endpoints of 256 bytes max, (one or two banks),

– 5 endpoints of 64 bytes max, (one or two banks)

21.2

Block Diagram

The USB controller provides the hardware to interface a USB link to a data flow stored in a dou-

ble port memory (DPRAM).

The USB controller requires a 48 MHz ±0.25% reference clock (for Full-Speed operation), which

is the output of an internal PLL. The PLL generates the internal high frequency (48 MHz) clock

for USB interface, the PLL input is generated from an external lower frequency (the crystal oscil-

lator or external clock input pin from XTAL1; to satisfy the USB frequency accuracy and jitter,

only this clock source allows proper functionnality of the USB controller).

The 48MHz clock is used to generate a 12 MHz Full-speed (or 1.5 MHz Low-Speed) bit clock

from the received USB differential data and to transmit data according to full or low speed USB

device tolerance. Clock recovery is done by a Digital Phase Locked Loop (DPLL) block, which is

compliant with the jitter specification of the USB bus.

To comply with the USB Electrical specification, USB Pads (D+ or D-) should be powered within

the 3.0 to 3.6V range. As ATmega32U6/AT90USB64/128 can be powered up to 5.5V, an inter-

nal regulator provides the USB pads power supply.

Figure 21-1. USB controller Block Diagram overview

CPU

USB Regulator

USB

Interface

PLL

24x

clk

2MHz

clk

48MHz

PLL clock

Prescaler

On-Chip

USB DPRAM

DPLL

Clock

Recovery

UCAP

D-

D+

VBUS

UID

UVCC

AVCC

XTAL1

AT90USB646 Datasheet(PDF) 246 Page - ATMEL Corporation

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