MODULE DESCRIPTION

TPS65950

Power subchip:

The SMPS have configurable output voltages. The LDO regulators provide power to internal analog and digital

circuits and to the external components. The output voltages of the external LDOs are also configurable.

The power resources also have configurable modes of operation. The possible modes for the power resources

are SLEEP, ACTIVE, and OFF. The modes and output values can be programmed using the I2C interface on the

TPS65950 device.

Programming for all the power resources is done through the I2C interface. The power subchip interfaces the

interface subchip and carries out commands to the rest of the device. The digital section has a finite

state-machine (FSM) that manages commands to the resources through the power bus.

Audio subchip:

The audio subchip has two interfaces: PCM for voice signaling and I2S for audio signaling. The Bluetooth

interface is also available. This uses the same clock and sync signals as for the PCM interface. Both ports can

function as master or slave.

Sampling modes available are:

Voice channel with 8-kHz or 16-kHz sampling modes

Audio channel with 8, 11.025, 12, 16, 22.05, 24, 32, 44.1, or 48-kHz sampling modes. 96 kHz is supported

on the RX path voice codec with MCLK = 26MHz.

The audio phase-locked loop (PLL) supports 26-MHz, 19.2-MHz, or 38.4-MHz ability to work with two ports with

the clock frequencies 19.2 MHz or 26 MHz, or with a single TDM port with the frequencies 19.2 MHz, 26 MHz, or

38.4 MHz. The voice PCM interface is available when the system clock is 26MHz.

The audio supports common features like pop-noise reduction, sidetone functionality, bass boost function, uplink

and downlink programmable gain amplifiers, and the DTMF tone generator.

The external vibrator control is provided in this module and can be controlled through an audio signal or direct

I2C writes to the registers.

USB subchip:

The primary function of the universal serial bus (USB) physical layer (PHY) is to transmit and receive USB data

at high speed (480M bit/s), full speed (12M bit/s), and low speed (1.5M bit/s). It also provides a pin-optimized

standard ULPI interface to a main USB controller device (LINK). In addition to the higher speeds, it supports

3-pin and 4-pin serial modes of operation.

The TPS65950 has a 5V-tolerant data line at all supported speeds. VBUS is tolerant up to 6 V. This device has

an on-chip 480MHz PLL from the internal system clock.

Auxiliary subchip:

The auxiliary subchip includes the following modules:

• Monitoring Analog-to-Digital Conversion (MADC)

• Battery Charger Interface (BCI)

• LED

• Keypad

MADC:

The MADC enables the host processors to monitor analog signals (such RF module temperature, battery

temperature, battery type, and battery level) using analog-to-digital conversion (ADC) on the input source. After

the conversion is complete, the host processor reads the results of the conversion through the I2C interface. The

MADC also performs analog signal conversion for other modules in the TPS65950: the BCI and the USB

subchip.

BCI:

The BCI can perform software-controlled linear charging with all the chargers it supports. The BCI can perform

software-controlled pulsed charging with current-limited ac chargers and automatic linear charging with ac

chargers, USB chargers, and carkits.

Copyright © 2008, Texas Instruments Incorporated

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Product Folder Link(s): TPS65950