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F71882FG Datasheet(PDF) 39 Page - Feature Integration Technology Inc.

Part # F71882FG
Description  Super Hardware Monitor LPC I/O
PDF  130 Pages
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Manufacturer  FINTEK [Feature Integration Technology Inc.]
Direct Link  http://www.fintek.com.tw/eng
Logo FINTEK - Feature Integration Technology Inc.

F71882FG Datasheet(HTML) 39 Page - Feature Integration Technology Inc.

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May, 2008
V0.28P
-33-
F71882
4
SELECT
R
-
Version of parallel port signal SLCT.
3
ERR_N
R
-
Version of parallel port signal ERR#.
2-1 Reserved
R
11
Reserved. Return 11b when read.
0
TMOUT
R
-
This bit is valid only in EPP mode. Return 1 when in other modes.
It indicates that a 10uS time out has occurred on the EPP bus.
0: no time out error.
1: time out error occurred, write 1 to clear.
Device Control Register
 Base + 2
Bit
Name
R/W Default
Description
7-6 Reserved
-
11
Reserved. Return 11b when read.
5
DIR
R/W
0
0: the parallel port is in output mode.
1: the parallel port is in input mode.
It is auto reset to 0 when in SPP mode.
4
ACKIRQ_EN
R/W
0
Enable an interrupt at the rising edge of ACK#.
3
SLIN
R/W
0
Inverted and then drives the parallel port signal SLIN#.
When read, the status of inverted SLIN# is return.
2
INIT_N
R/W
0
Drives the parallel port signal INIT#.
When read, the status of INIT# is return.
1
AFD
R/W
0
Inverted and then drives the parallel port signal AFD#.
When read, the status of inverted AFD# is return.
0
STB
R/W
0
Inverted and then drives the parallel port signal STB#.
When read, the status of inverted STB# is return.
EPP Address Register
 Base + 3
Bit
Name
R/W Default
Description
7-0 EPP_ADDR
R/W
00h
Write this register will cause the hardware to auto transmit the written data to
the device with the EPP Address Write protocol.
Read this register will cause the hardware to auto receive data from the device
by with the EPP Address Read protocol.
EPP Data Register
 Base + 4 – Base + 7
Bit
Name
R/W Default
Description
7-0 EPP_DATA
R/W
00h
Write this register will cause the hardware to auto transmit the written data to
the device with the EPP Data Write protocol.
Read this register will cause the hardware to auto receive data from the device
by with the EPP Data Read protocol.
Parallel Port Data FIFO
 Base + 400h
Bit
Name
R/W Default
Description



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