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LT1713/LT1714

APPLICATIO S I FOR ATIO

Common Mode Considerations

The LT1713/LT1714 are specified for a common mode

range of – 5.1V to 5.1V on a

±5V supply, or a common

mode range of – 0.1V to 5.1V on a single 5V supply. A more

general consideration is that the common mode range is

from 100mV below the negative supply to 100mV above

the positive supply, independent of the actual supply volt-

age. The criteria for common mode limit is that the output

still responds correctly to a small differential input signal.

When either input signal falls outside the common mode

limit, the internal PN diode formed with the substrate can

turn on resulting in significant current flow through the

die. Schottky clamp diodes between the inputs and the

supply rails speed up recovery from excessive overdrive

conditions by preventing these substrate diodes from

turning on.

Input Bias Current

Input bias current is measured with the outputs held at

2.5V with a 5V supply voltage. As with any rail-to-rail

differential input stage, the LT1713/LT1714 bias current

flows into or out of the device depending upon the com-

mon mode level. The input circuit consists of an NPN pair

and a PNP pair. For inputs near the negative rail, the NPN

pair is inactive, and the input bias current flows out of the

device; for inputs near the positive rail, the PNP pair is

inactive, and these currents flow into the device. For inputs

far enough away from the supply rails, the input bias

current will be some combination of the NPN and PNP bias

currents. As the differential input voltage increases, the

input current of each pair will increase for one of the inputs

and decrease for the other input. Large differential input

voltages result in different input currents as the input

stage enters various regions of operation. To reduce the

influence of these changing input currents on system

operation, use a low source resistance.

Latch Pin Dynamics

The internal latches of the LT1713/LT1714 comparators

retain the input data (output latched) when their respective

latch pin goes high. The latch pin will float to a low state

when disconnected, but it is better to ground the latch

when a flow-through condition is desired. The latch pin is

designed to be driven with either a TTL or CMOS output.

It has built-in hysteresis of approximately 100mV, so that

slow moving or noisy input signals do not impact latch

performance. For the LT1714, if only one of the compara-

tors is being used at a given time, it is best to latch the

second comparator to avoid any possibility of interactions

between the two comparators in the same package.

High Speed Design Techniques

A substantial amount of design effort has made the

LT1713/LT1714 relatively easy to use. As with most high

speed comparators, careful attention to PC board layout

and design is important in order to prevent oscillations.

The most common problem involves power supply by-

passing which is necessary to maintain low supply im-

pedance. Resistance and inductance in supply wires and

PC traces can quickly build up to unacceptable levels,

thereby allowing the supply voltages to move as the

supply current changes. This movement of the supply

voltages will often result in improper operation. In addi-

tion, adjacent devices connected through an unbypassed

supply can interact with each other through the finite

supply impedances.

Bypass capacitors furnish a simple solution to this prob-

lem by providing a local reservoir of energy at the device,

thus keeping supply impedance low. Bypass capacitors

should be as close as possible to the LT1713/LT1714

supply pins. A good high frequency capacitor, such as a

0.1

µF ceramic, is recommended in parallel with a larger

capacitor, such as a 4.7

µF tantalum.

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