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HV66X Datasheet(PDF) 2 Page - Supertex, Inc |
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HV66X Datasheet(HTML) 2 Page - Supertex, Inc |
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2 / 6 page ![]() 2 Symbol Parameter Min Max Units V DD Logic supply voltage 4.5 5.5 V V PP Output voltage* 0 32 V VIH High-level input voltage 2.4 VDD V V IL Low-level input voltage 0 0.8 V f CLK Clock frequency 0 5 MHz TA Operating free-air temperature -40 +85 °C I OD Allowable current through output diodes 200 mA Notes: *Output will not switch below 12V. Power-up sequence should be the following: 1. Connect ground. 3. Set all inputs (Data, CLK, Enable, etc.) to a known state. 2. Apply VDD.4. Apply VPP. Power-down sequence should be the reverse of the above. The VPP should not drop below VDD during operation. Electrical Characteristics (over recommended operating conditions unless noted) DC Characteristics (V DD = 5V, VPP = 32V, VSS = GND) Symbol Parameter Min Max Units Conditions I DD V DD supply current 15 mA V DD = VDD max f CLK = 5MHz I PPQ High voltage supply current 0.5 mA Outputs high 0.5 mA Outputs low I DDQ Quiescent V DD supply current 0.5 mA All V IN = VSS or VDD V OH High-level output Q 22 V I O= 1mA, VPP = 24V Data out 4.6 V IO= -100µA V OL Low-level output Q 2 V I O= 1mA Data out 0.4 V I O= 100µA IIH High-level logic input current 1 µAVIH = VDD I IL Low-level logic input current -1 µAVIL = 0V V OLBP Low-level output voltage, backplane 3 V I O = 10mA VOHBP High-level output voltage, backplane 29 V IO = -10mA AC Characteristics (V DD = 5V, VPP = 32V, TC = 25°C), logic input rises/fall time = 10ns. Symbol Parameter Min Max Units Conditions f CLK Clock frequency 5 MHz tW Clock width high or low 100 ns tSU Data set-up time before clock rises 25 ns t H Data hold time after clock rises 50 ns tON, tOFF Time from latch enable or POL to HVOUT 500 ns CL = 20pF t ON, tOFF Time from POL to BP output 500 ns C L = 20pF t DHL Delay time clock to data high to low 200 ns C L = 10pF tDLH Delay time clock to data low to high 200 ns CL = 10pF t DLE Delay time clock to LE low to high 50 ns t WLE Width of LE pulse 100 ns tSLE LE set-up time before clock rises 50 ns t BR, tBF BP OUT rise/fall time 10 1000 µsCL = 350nF tBR - tBF BP OUT rise and fall difference 100 µsCL = 350nF Recommended Operating Conditions HV66 |
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