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AT52SC1283J Datasheet(PDF) 34 Page - ATMEL Corporation |
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AT52SC1283J Datasheet(HTML) 34 Page - ATMEL Corporation |
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34 / 52 page ![]() 34 3530B–STKD–2/4/05 AT52SC1283J/1284J [Preliminary] 28. Four-word Burst Read Waveform (Clock Latency of 4) Note: 1. The WAIT signal shown is for a burst configuration register of B10 and B8 = 1. 29. Burst Suspend Waveform Notes: 1. The WAIT signal (dashed line) shown is for a burst configuration register setting of B10 and B8 = 0. The WAIT Signal (solid line) shown is for a burst configuration setting of B10 = 1 and B8 = 0. 2. During Burst Suspend, CLK signal can be held low or high. CE A0-A22 I/O0-I/O15 AVD CLK OE VALID A C B WAIT (1) HIGH Z HIGH Z D0 D2 D3 D1 D0 D1 D2 D1 CE I/O0-I/O15 A0-A22 AVD CLK OE tCLK tCKH tCKL ... WAIT tCEAV tCE tAHAV tAAV tCECK tAHCK tAVCK tACK tCKAV tCKQV tCEQZ tQHCK tDF (2) (2) tOE |
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