LT1719CS8 datasheet(14/20 Pages) LINER

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LT1719

APPLICATIONS INFORMATION

Circuit Description

The block diagram of the LT1719 is shown in Figure 7. The

circuit topology consists of a differential input stage, a

gain stage with hysteresis and a complementary com-

mon-emitter output stage. All of the internal signal paths

utilize low voltage swings for high speed at low power.

The input stage topology maximizes the input dynamic

range available without requiring the power, complexity

and die area of two complete input stages such as are

found in rail-to-rail input comparators. With a single 2.7V

supply, the LT1719 still has a respectable 1.6V of input

common mode range. The differential input voltage range

is rail-to-rail, without the large input currents found in

competing devices. The input stage also features phase

reversal protection to prevent false outputs when the

inputs are driven below the –100mV common mode

voltage limit.

The internal hysteresis is implemented by positive, nonlin-

ear feedback around a second gain stage. Until this point,

the signal path has been entirely differential. The signal

path is then split into two drive signals for the upper and

lower output transistors. The output transistors are con-

nected common emitter for rail-to-rail output operation.

The Schottky clamps limit the output voltages at about

300mV from the rail, not quite the 50mV or 15mV of Linear

Technology’s rail-to-rail ampliﬁers and other products.

But the output of a comparator is digital, and this output

stage can drive TTL or CMOS directly. It can also drive ECL,

as described earlier, or analog loads as demonstrated in

the applications to follow.

The bias conditions and signal swings in the output stage

are designed to turn their respective output transistors off

faster than on. This helps minimize the surge of current

from + VS/V+ to ground that occurs at transitions, to

minimize the frequency-dependent increase in power con-

sumption. The frequency dependence of the supply cur-

rent is shown in the Typical Performance Characteristics.

OUT

GND OR V –

+VS OR V

–

+IN

–IN

AV1

VCC OR V

VEE OR V

–

SHUTDOWN

AV2

NONLINEAR STAGE

1719 F07

BIAS CONTOL

Figure 7. LT1719 Block Diagram

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