LT1719CS6 datasheet(10/20 Pages) LINER

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LT1719

shutdown is active high, this resistor adds little power

drain during shutdown. A logic high disables the compara-

tor. The LT1719S8 logic interface is based on the output

power rails, + VS and GND.

For applications that do not use the shutdown feature, it

may be helpful to tie the shutdown control to ground

through a 100

Ω resistor rather than directly. This allows

the SHDN pin to be pulled high during debug or in-circuit

test (bed of nails) so that the output node can be wiggled

without damaging the low impedance output driver of the

LT1719.

The shutdown state is not guaranteed to be useful as a

multiplexer. Digital signals can have extremely fast edge

rates that may be enough to momentarily activate the

LT1719 output stage via internal capacitive coupling. No

damage to the LT1719 will result, but this could prove

deleterious to the intended recipient of the signal.

The LT1719 includes a FET pull-up on the shutdown

control pin (see Simplified Schematic) as well as other

internal structures to make the shutdown state current

drain <<1

µA. Shutdown is guaranteed with an open circuit

on the shutdown control pin. When the shutdown control

pin is driven to + VS/V+ – 0.5V, the 70kΩ linear region

impedance of the pull-up FET will cause a current flow of

µA (typ) into the +VS/V+ pin and out the shutdown pin.

Currents in all other power supply terminals will be <1

µA.

Power Supply Sequencing

The LT1719S8 is designed to tolerate any power supply

sequencing at system turn-on and power down. In any of

the previously shown power supply configurations, the

various supplies can activate in any order without exces-

sive current drain by the LT1719.

As always, the Absolute Maximum Ratings must not be

exceeded, either on the power supply terminals or the

input terminals. Power supply sequencing problems can

occur when input signals are powered from supplies that

are independent of the LT1719’s supplies. For the com-

parator inputs, the signals should be powered from the

same VCC and VEE supplies as the LT1719. For the shut-

down input, the signal should be powered from the same

+VS as the LT1719.

APPLICATIONS INFORMATION

Hysteresis

The LT1719 includes internal hysteresis, which makes it

easier to use than many other similar speed comparators.

The input-output transfer characteristic is illustrated in

Figure 3 showing the definitions of VOS and VHYST based

upon the two measurable trip points. The hysteresis band

makes the LT1719 well behaved, even with slowly moving

inputs.

Figure 3. Hysteresis I/O Characteristics

VHYST

(= VTRIP

+ – V

TRIP

–)

VHYST/2

VOL

1719 F03

VOH

VTRIP

–

VTRIP

∆VIN = VIN+ – VIN–

VTRIP

+ + V

TRIP

–

VOS =

The exact amount of hysteresis will vary from part to part

as indicated in the specifications table. The hysteresis

level will also vary slightly with changes in supply voltage

and common mode voltage. A key advantage of the

LT1719 is the significant reduction in these effects, which

is important whenever an LT1719 is used to detect a

threshold crossing in one direction only. In such a case,

the relevant trip point will be all that matters, and a stable

offset voltage with an unpredictable level of hysteresis, as

seen in competing comparators, is useless. The LT1719 is

many times better than prior comparators in these re-

gards. In fact, the CMRR and PSRR tests are performed by

checking for changes in either trip point to the limits

indicated in the specifications table. Because the offset

voltage is the average of the trip points, the CMRR and

PSRR of the offset voltage is therefore guaranteed to be at

least as good as those limits. This more stringent test also

puts a limit on the common mode and power supply

dependence of the hysteresis voltage.

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