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LT1976/LT1976B

1976bfg

APPLICATIO S I FOR ATIO

See the Typical Performance Characteristics section for

graphs of SHDN and VIN currents verses input voltage.

SYNCHRONIZING

Oscillator synchronization to an external input is achieved

by connecting a TTL logic-compatible square wave with a

duty cycle between 20% and 80% to the LT1976 SYNC

pin. The synchronizing range is equal to initial operating

frequency up to 700kHz. This means that minimum

practical sync frequency is equal to the worst-case high

self-oscillating frequency (230kHz), not the typical oper-

ating frequency of 200kHz. Caution should be used when

synchronizing above 230kHz because at higher sync

frequencies the amplitude of the internal slope compen-

sation used to prevent subharmonic switching is re-

duced. This type of subharmonic switching only occurs at

input voltages less than twice output voltage. Higher

inductor values will tend to eliminate this problem. See

Frequency Compensation section for a discussion of an

entirely different cause of subharmonic switching before

assuming that the cause is insufficient slope compensa-

tion. Application Note 19 has more details on the theory

of slope compensation.

If the FB pin voltage is below 0.9V (power-up or output

short-circuit conditions) the sync function is disabled.

This allows the frequency foldback to operate to avoid and

hazardous conditions for the SW pin.

If the synchronization signal is present during Burst Mode

operation, synchronization will occur during the burst

portion of the output waveform. Synchronizing the LT1976

during Burst Mode operation may alter the natural burst

frequency which can lead to jitter and increased ripple in

the burst waveform. Synchronizing the LT1976B during

pulse skip operation may also increase output ripple.

If no synchronization is required this pin should be con-

nected to ground.

POWER GOOD

The LT1976 contains a power good block which consists

of a comparator, delay timer and active low flag that allows

the user to generate a delayed signal after the power good

threshold is exceeded.

Referring to Figure 2, the PGFB pin is the positive input to

a comparator whose negative input is set at VPGFB. When

PGFB is taken above VPGFB, current (ICSS) is sourced into

the CT pin starting the delay period. When the voltage on

the PGFB pin drops below VPGFB the CT pin is rapidly

discharged resetting the delay period. The PGFB voltage is

typically generated by a resistive divider from the regu-

lated output or input supply.

The capacitor on the CT pin determines the amount of

delay time between the PGFB pin exceeding its threshold

(VPGFB) and the PG pin set to a high impedance state.

When the PGFB pin rises above VPGFB current is sourced

Figure 8. Undervoltage Lockout

ENABLE

1.3V

1976 F08

μA

SHDN

2.4V

–

SHDN

COMP

–

VIN

COMP

VIN

VOUT

LT1976

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