Features

Parallel interface support for 8-bit

Pre-processed capture modes:

YCbCr 4:2:2 data format

GRB 4:2:2, RGB 565, RGB 555, RGB 444 data formats

Programmable vertical and horizontal resolution

Programmable polarity of frame clock & line clock

Deliverables

Technical Specification

RTL Verilog Synthesizable Code

Comprehensive Test Environment

Technical Support and Maintenance

Core Benefits

Can be used in all kind of video processing applications

iW-Camera Interface core accepts pre-processed, synchronized frames in 10-bit YCbCr / RGB format from a digital camera

and outputs 10-bit video data in the same format in a continuous stream without blanking and synchronization information for

downstream processing.

Overview

Block Diagram

Control

Register

FIFO

pclk_i

hsync_i

vsync_i

pdat_i[7:0]

pixelout_o[7:0]

pixelout_vld_o

cn_we_i

cn_data_i[31:0]

cn_addr_i[1:0]

clk_i

pixelout_rdy_i

Pixel Output Interface

Pixel Output Interface

System Interface

System Interface

Control Interface

Control Interface

rst_n_i

Camera Interface

Camera Interface

cn_oe_i

cn_data_o[31:0]

FSM

soi_o

eoi_o

Core Applications

By integrating with digital cameras this can be used in remote monitoring systems, security systems and etc.

Resource Utilization Summary

Actel

Family

Device

Cores

RAM

IO

PLL

Fmax

(MHz)

ProASIC3

A3P250

1261

1

104

0

63

IGLOO

AGL600

1243

1

104

0

32