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The EP100 PowerPC bus slave device is a bus interface unit designed for the

PowerPC host bus. It is designed to work on any 60x compliant bus architecture.

It has two user interfaces, one for interfacing with on-chip and off-chip user logic

and register and the second interface is a direct interface to external asynchronous

SRAM and synchronous BURST SRAM.

The PowerPC slave works together with other devices or system controllers on the

PowerPC bus. The slave can be assigned to a specific address space where it is

mapped into. Access to the slave device is further directed to either the SRAM

interface or the user interface bus based on address mapping. The address map-

ping controller can be hardwired to the core or can be supplied by the user during

run-time. The slave supports both the regular data transfer size and also the

extended data transfer size specific to MPC8260.

The slave handles address pipeline on the PowerPC bus with up to 2 outstanding

requests. While the slave is processing data transfer of one request, the CPU can

start the address tenure of a second request. Address retry and separate address

and data bus tenure are also supported by the slave. The slave detects data bus

grant and data bus busy before starting its data tenure.

The following table summarizes the optional features which can be provided with

the core as required by user application.

Options

Description

SRAM speed

Different SRAM access speed can be pro-

grammed as wait states.

Pipeline or flow-through

burst SRAM

Support both types of burst SRAM.

Bus sharing

Sharing the CPU bus with MPC106/107

Data parity

Supports PowerPC data parity

Multiple address mapping

Address space mapping to support multiple

user logic devices.

Family

Device

Utilization

Performance

(-speed grade)

SEQ

COMB

Total

RAM

ProASICPlus

APA150-STD

584

1566

35%

50Mhz

Axcelerator

AX500-3

620

534

15%

99Mhz

RTSX-S

RT54SX32S-2

618

548

41%

47Mhz

OPTIONAL

FEATURES

EP100 PowerPC Bus Slave

Actel Device

Utilization

Data

DESCRIPTIONS