LTC1606CSW datasheet(7/16 Pages) LINER

7 / 16 page

LTC1606

1606fa

VIN (Pin 1): Analog Input. Connect through a 200Ω

resistor to the analog input. Full-scale input range is

±10V.

AGND1 (Pin 2): Analog Ground. Tie to analog ground

plane.

REF (Pin 3): 2.5V Reference Output. Bypass with 2.2

µF

tantalum capacitor. Can be driven with an external

reference.

CAP (Pin 4): Reference Buffer Output. Bypass with 10

µF

tantalum capacitor. The capacitor output voltage is 4.096V

when REF = 2.5V.

AGND2 (Pin 5): Analog Ground. Tie to analog ground

plane.

D15 to D8 (Pins 6 to 13): Three-State Data Outputs.

Hi-Z state when CS is high or when R/C is low.

DGND (Pin 14): Digital Ground.

D7 to D0 (Pins 15 to 22): Three-State Data Outputs.

Hi-Z state when CS is high or when R/C is low.

BYTE (Pin 23): Byte Select. With BYTE low, data will be

output with Pin 6 (D15) being the MSB and Pin 22 (D0)

being the LSB. With BYTE high, the upper eight bits and

the lower eight bits will be switched. The MSB is output

on Pin 15 and bit 8 is output on Pin 22. Bit 7 is output on

Pin 6 and the LSB is output on Pin 13.

R/C (Pin 24): Read/Convert Input. With CS low, a falling

edge on R/C puts the internal sample-and-hold into the

hold state and starts a conversion. With CS low, a rising

edge on R/C enables the output data bits.

CS (Pin 25): Chip Select. Internally OR’d with R/C. With

R/C low, a falling edge on CS will initiate a conversion.

With R/C high, a falling edge on CS will enable the output

data.

BUSY (Pin 26): Output Shows Converter Status. It is low

when a conversion is in progress. Data valid on the rising

edge of BUSY. CS or R/C must be high when BUSY rises

or another conversion will start without time for signal

acquisition.

VANA (Pin 27): 5V Analog Supply. Bypass to ground with

a 0.1

µF ceramic and a 10µF tantalum capacitor.

VDIG (Pin 28): 5V Digital Supply. Connect directly to

Pin 27.

PI FU CTIO S

16-BIT CAPACITIVE DAC

COMP

REF BUF

1.64x

2.5V REF

CAP

(4.096V)

CSAMPLE

•

D15

BUSY

CONTROL LOGIC

R/C

BYTE

INTERNAL

CLOCK

ZEROING SWITCHES

VDIG

VANA

VIN

REF

AGND1

AGND2

DGND

1606 BD

–

SUCCESSIVE APPROXIMATION

OUTPUT LATCHES

7.35k

2.5k

FU CTIO AL BLOCK DIAGRA

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