LTC2481CDD datasheet(13/40 Pages) LINER

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LTC2481

2481f

APPLICATIO S I FOR ATIO

Figure 2. Definition of Timing for F/S-Mode Devices on the I2C-Bus

The LTC2481 can only be addressed as a slave. Once

addressed, it can receive configuration bits or transmit the

last conversion result. Therefore the serial clock line SCL

is an input only and the data line SDA is bidirectional. The

device supports the Standard-mode and the Fast-mode

for data transfer speeds up to 400kbit/s. Figure 2 shows

the definition of timing for Fast/Standard-mode devices

on the I2C-bus.

The START and STOP Conditions

A START condition is generated by transitioning SDA from

HIGH to LOW while SCL is HIGH. The bus is considered to

be busy after the START condition. When the data transfer

is finished, a STOP condition is generated by transitioning

SDA from LOW to HIGH while SCL is HIGH. The bus is free

again a certain time after the STOP condition. START and

STOP conditions are always generated by the master.

When the bus is in use, it stays busy if a repeated START

(Sr) is generated instead of a STOP condition. The

repeated START (Sr) conditions are functionally identical

to the START (S).

Data Transferring

After the START condition, the I2C bus is busy and data

transfer is set between a master and a slave. Data is

transferred over I2C in groups of nine bits (one byte)

followed by an acknowledge bit, therefore each group

takes nine SCL cycles. The transmitter releases the SDA

line during the acknowledge clock pulse and the receiver

issues an Acknowledge (ACK) by pulling SDA LOW or

leaves SDA HIGH to indicate a Not Acknowledge (NAK)

condition. Change of data state can only happen while SCL

is LOW.

Accessing the Special Features of the LTC2481

The LTC2481 combines a high resolution, low noise

∆Σ

analog-to-digital converter with an on-chip selectable tem-

perature sensor, programmable gain, programmable digital

filter and output rate control. These special features are

selected through a single 8-bit serial input word during the

data input/output cycle (see Figure 3).

The LTC2481 powers up in a default mode commonly

used for most measurements. The device will remain in

this mode until a valid write cycle is performed. In this

default mode, the measured input is external, the GAIN is

1, the digital filter simultaneously rejects 50Hz and 60Hz

line frequency noise, and the speed mode is 1x (offset

automatically, continuously calibrated).

The I2C serial interface grants access to any or all special

functions contained within the LTC2481. In order to

change the mode of operation, a valid write address

followed by 8 bits of data are shifted into the device (see

Table 1). The first 3 bits (GS2, GS1, GS0) control the

GAIN of the converter from 1 to 256. The 4th bit is

reserved and should be low. The 5th bit (IM) is used to

select the internal temperature sensor as the conversion

input, while the 6th and 7th bits (FA, FB) combine to

determine the line frequency rejection mode. The 8th bit

(SPD) is used to double the output rate by disabling the

offset auto calibration.

SDA

SCL

SSr

tLOW

tHD;STA

tBUF

tSP

tSU;STA

tSU;STO

tHD;DAT

tHIGH

tSU;DAT

2481 F02

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