LTC2923IDE datasheet(11/20 Pages) LINER

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LTC2923

2923fa

APPLICATIO S I FOR ATIO

3-Step Design Procedure

The following 3-step procedure allows one to complete a

design for any of the tracking or sequencing profiles

shown in Figures 1 to 4. A basic three supply application

circuit is shown in Figure 9.

Set the ramp rate of the master signal.

Solve for the value of CGATE, the capacitor on the GATE

pin, based on the desired ramp rate (V/s) of the master

supply, SM.

GATE

≈

where IGATE 10

(1)

If the external FET has a gate capacitance comparable to

CGATE, then the external capacitor’s value should be

reduced to compensate for the FET’s gate capacitance.

If no external FET is used, tie the GATE and RAMP pins

together.

Solve for the pair of resistors that provide the desired

ramp rate of the slave supply, assuming no delay.

Choose a ramp rate for the slave supply, SS. If the slave

supply ramps up coincident with the master supply or

with a fixed voltage offset, then the ramp rate equals the

master supply’s ramp rate. Be sure to use a fast enough

ramp rate for the slave supply so that it will finish

ramping before the master supply has reached its final

supply value. If not, the slave supply will be held below

the intended regulation value by the master supply. Use

the following formulas to determine the resistor values

for the desired ramp rate, where RFB and RFA are the

feedback resistors in the slave supply and VFB is the

feedback reference voltage of the slave supply:

•

(2)

TRACK

′ =

–

(3)

where VTRACK ≈ 0.8V.

Note that large ratios of slave ramp rate to master ramp

rate, SS/SM, may result in negative values for RTA′. If

sufficiently large delay is used in step 3, RTA will be

positive, otherwise SS/SM must be reduced.

Choose RTA to obtain the desired delay.

If no delay is required, such as in coincident and

ratiometric tracking, then simply set RTA = RTA′. If a

delay is desired, as in offset tracking and supply se-

quencing, calculate RTA′′ to determine the value of RTA

where tD is the desired delay in seconds.

TRACK

′′ =

•

(4)

RTA = RTA′||RTA′′

(5)

the parallel combination of RTA′ and RTA′′

As noted in step 2, small delays and large ratios of slave

ramp rate to master ramp rate (usually only seen in

sequencing) may result in solutions with negative values

for RTA. In such cases, either the delay must be increased

or the ratio of slave ramp rate to master ramp rate must be

reduced.

Figure 9. Three Supply Application

CGATE

VCC

RONB

VIN

RTB1

RTB2

RFA1

SLAVE1

MASTER

RFB1

RTA2

RTA1

RONA

FB1

GATE

LTC2923

GND

2923 F09

RAMP

RFA2

SLAVE2

RFB2

RAMPBUF

TRACK1

TRACK2

FB2

DC/DC

VIN

OUT

DC/DC

OUT

0.1µF

10Ω

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