P-Channel Logic Level E nhancement Mode Field E ffect Transistor

Mar,29, 2007

S amHop Microelectronics C orp.

P R ODUC T S UMMAR Y

-40A

-40V

S T U/D419S

S TU S E R IE S

TO-252AA(D-PAK)

S TD S E R IE S

TO-251(l-PAK)

G

G

G

G

SS

SS

D

D

D

D

Parameter

S ymbol

Unit

Drain-S ource Voltage

V

Gate-S ource Voltage

V

Drain Current-Continuous @ Ta

-Pulsed

50

A

A

A

W

Drain-S ource Diode Forward Current

Maximum Power Dissipation

Operating Junction and S torage

Temperature R ange

-55 to 175

C

a

a

a

b

-40

-10

20

-40

-100

25 C

70 C

Ta= 25 C

Ta=70 C

35

-32

A

Limit

THE R MAL CHAR ACTE R IS TICS

Thermal R esistance, Junction-to-Case

Thermal R esistance, Junction-to-Ambient

3

50

/W

C

/W

C

AB S OLUTE MAXIMUM R ATINGS

S urface Mount Package.

F E AT UR E S

R ugged and reliable.

E S D Procteced

W

S

G

D

1