BQ4285S- datasheet(2/27 Pages) TI

Part #	BQ4285S-

Description	Real-Time Clock RTC With NVRAM Control

PDF	27 Pages

Scroll/Zoom	100%

Manufacturer	TI [Texas Instruments]

Direct Link	http://www.ti.com

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2 / 27 page

Block Diagram

Pin Descriptions

AD0–AD7

Multiplexed address/data input/

output

The bq4285 bus cycle consists of two

phases: the address phase and the data-

transfer phase.

The address phase pre-

cedes the data-transfer phase. During the

address

phase,

address

placed

AD0–AD7 is latched into the bq4285 on the

falling edge of the AS signal.

During the

data-transfer phase of the bus cycle, the

AD0–AD7 pins serve as a bidirectional data

bus.

MOT

Connect to VSS for correct operation

Chip select input

CS should be driven low and held stable

during the data-transfer phase of a bus cy-

cle accessing the bq4285.

Bus

Type

MOT

Level

Equivalent

R/W

Equivalent

Intel

VSS

RD,

MEMR,

or I/OR

WR,

MEMW,

or I/OW

ALE

Table 1. Bus Setup

bq4285

BQ4285S- Datasheet(PDF) 2 Page - Texas Instruments

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