CD74HC393 datasheet(1/8 Pages) TI

Part #	CD74HC393

Description	High Speed CMOS Logic Dual 4 -Stage Binary Counter

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Data sheet acquired from Harris Semiconductor

SCHS186

Features

• Fully Static Operation

• Buffered Inputs

• Common Reset

• Negative-Edge Clocking

• Typical fMAX = 60 MHz at VCC = 5V, CL = 15pF,

TA = 25

oC

• Fanout (Over Temperature Range)

- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55oC to 125oC

• Balanced Propagation Delay and Transition Times

• Signiﬁcant Power Reduction Compared to LSTTL

Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: NIL = 30%, NIH = 30%of VCC at

VCC = 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

VIL= 0.8V (Max), VIH = 2V (Min)

- CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH

Description

The Harris CD74HC393 and CD74HCT393 are 4-stage

ripple-carry binary counters. Al counter stages are master-

slave ﬂip-ﬂops. The state of the stage advances one count

on the negative transition of each clock pulse; a high voltage

level on the MR line resets all counters to their zero state. All

inputs and outputs are buffered.

Pinout

CD74HC393, CD74HCT393

(PDIP, SOIC)

TOP VIEW

Ordering Information

PART NUMBER

TEMP. RANGE (oC)

PACKAGE

PKG.

NO.

CD74HC393E

-55 to 125

14 Ld PDIP

E14.3

CD74HCT393E

-55 to 125

14 Ld PDIP

E14.3

1CP

1MR

1Q0

1Q1

1Q2

1Q3

GND

VCC

2CP

2MR

2Q0

2Q1

2Q2

2Q3

1

2

3

4

5

6

7

14

13

12

11

10

9

8

September 1997

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

Copyright

File Number

1653.1

CD74HC393,

CD74HCT393

High Speed CMOS Logic

Dual 4 -Stage Binary Counter

[ /Title

(CD74

HC393

,

CD74

HCT39

3)

/Sub-

ject

(High

Speed

CMOS

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