1

Data sheet acquired from Harris Semiconductor

SCHS187

Features

• Common Latch-Enable Control

• Common Three-State Output Enable Control

• Buffered Inputs

• Three-State Outputs

• Bus Line Driving Capacity

• Fanout (Over Temperature Range)

- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Balanced Propagation Delay and Transition Times

• Significant Power Reduction Compared to LSTTL

Logic ICs

• HC Types

- 2V to 6V Operation

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

Description

The Harris CD74HC533, CD74HCT533, CD74HC563, and

CD74HCT563 are high speed Octal Transparent Latches

manufactured with silicon gate CMOS technology. They pos-

sess the low power consumption of standard CMOS inte-

grated circuits, as well as the ability to drive 15 LSTTL

devices.

The outputs are transparent to the inputs when the latch

enable (LE) is high. When the latch enable (LE) goes low the

data is latched. The output enable (OE) controls the three-

state outputs. When the output enable (OE) is high the

outputs are in the high impedance state. The latch operation

is independent to the state of the output enable.

The CD74HC533 and CD74HCT533 are identical in function

to the CD74HC563 and CD74HCT563 but have different

pinouts. The CD74HC533 and CD74HCT533 are similar to

the CD74HC373 and CD74HCT373; the latter are non-

inverting types.

Ordering Information

PART NUMBER

TEMP. RANGE

PACKAGE

PKG.

NO.

CD74HC533E

-55 to 125

20 Ld PDIP

F20.3

CD74HCT533E

-55 to 125

20 Ld PDIP

E20.3

CD74HC563E

-55 to 125

20 Ld PDIP

E20.3

CD74HCT563E

-55 to 125

20 Ld PDIP

E20.3

CD74HCT563M

-55 to 125

20 Ld SOIC

M20.3

NOTES:

1. When ordering, use the entire part number. Add the suffix 96 to

obtain the variant in the tape and reel.

2. Wafer and die for this part number are available which meets all

electrical specifications. Please contact your local sales office or

Harris customer service for ordering information.

January 1998

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

Copyright

CD74HC533, CD74HCT533,

CD74HC563, CD74HCT563

High Speed CMOS Logic Octal Inverting

Transparent Latch, Three-State Outputs

File Number

1599.1

[ /Title

(CD74H

C533,

CD74H

CT533,

CD74H

C563,

CD74H

CT563)

/Subject

(High

Speed