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CDC857-2 Datasheet(PDF) 7 Page - Texas Instruments |
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CDC857-2 Datasheet(HTML) 7 Page - Texas Instruments |
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7 / 12 page ![]() CDC857-2, CDC857-3 2.5-/3.3-V PHASE-LOCK LOOP CLOCK DRIVERS SCAS627A – SEPTEMBER 1999 – DECEMBER 1999 7 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 APPLICATION EXAMPLE Table 1. Clock Structure and SDRAM Loads per Clock CLOCK STRUCTURE NUMBER of SDRAM LOADS CAPACITIVE LOADING ON THE PLL OUTPUTS (pF) STRUCTURE PER CLOCK MIN MAX 1 2 5 8 2 4 10 16 PLL SDRAM SDRAM ≈ 2.5” ≈ 0.6” (Split to Terminator) 0.3” 120 Ω CLK CLK VTR VCP SDRAM represents a capacitive load 120 Ω 16 pF 120 Ω 16 pF FBIN FBIN Figure 1. Clock Structure #1 |
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