PCA8550

NONVOLATILE 5-BIT REGISTER

SCPS050A – MARCH 1999 – REVISED APRIL 1999

5

POST OFFICE BOX 655303

nonvolatile storage specifications

PARAMETER

SPECIFICATIONS

Write time (twr)

10 ms, typical

Memory-cell data retention

10 years, minimum

Maximum number of memory-cell write cycles

1000 cycles, minimum

otherwise noted) (see Figure 1)

VCC = 3.3 V ± 0.3 V

UNIT

MIN

MAX

UNIT

fscl

I2C clock frequency

10

400

kHz

Tsch

I2C clock high time

600

ns

Tscl

I2C clock low time

1.3

µs

Tsp

I2C spike time

0

50

ns

Tsds

I2C serial data setup time

100

ns

Tsdh

I2C serial data hold time

0

900

ns

Ticr

I2C input rise time

20

300

ns

Ticf

I2C input fall time

20

300

ns

Tocf

I2C output fall time (10-pF to 400-pF bus)

20 + 0.1 Cb†

250

ns

Tbuf

I2C bus free time between stop and start

1.3

µs

Tsts

I2C start or repeated start condition setup

600

ns

Tsth

I2C start or repeated start condition hold

600

ns

Tsps

I2C stop condition setup

600

ns

Cb†

I2C bus capacitive load

400

pF

† Cb = capacitance of one bus line in pF.

switching characteristics over recommended operating free-air temperature range (unless

otherwise noted) (see Figure 2)

PARAMETER

FROM

(INPUT)

TO

(OUTPUT)

VCC = 3.3 V

± 0.3 V

UNIT

(INPUT)

(OUTPUT)

MIN

MAX

tmpd

Mux input to output

propagation delay

MUX IN

MUX OUT

20

ns

tsov

MUX SELECT to output valid

MUX SELECT

Output valid

22

ns

tovn

OVERRIDE to NON-MUXED

OUT output delay

OVERRIDE

NON-MUXED OUT

15

ns

tovm

OVERRIDE to MUX OUT

output delay

OVERRIDE

MUX OUT

25

ns

tsu

Setup time

WP

Falling edge of first valid data byte

acknowledge on the SCL input

30

ns

th

Hold time

WP

Falling edge of first valid data byte

acknowledge on the SCL input

120

ns

tr

Output rise time

1

3

ns/V

tf

Output fall time

1

3

ns/V