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LPC1765 Datasheet(PDF) 13 Page - NXP Semiconductors

Part # LPC1765
Description  32-bit ARM Cortex-M3 microcontroller up to 512 kB flash and 64 kB SRAM with Ethernet, USB 2.0 Host/Device/OTG, CAN
PDF  72 Pages
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Manufacturer  PHILIPS [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

LPC1765 Datasheet(HTML) 13 Page - NXP Semiconductors

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LPC1768_66_65_64_2
© NXP B.V. 2009. All rights reserved.
Objective data sheet
Rev. 02 — 11 February 2009
13 of 72
NXP Semiconductors
LPC1768/66/65/64
32-bit ARM Cortex-M3 microcontroller
P3[26]/STCLK/
MAT0[1]/PWM1[3]
26[1]
I/O
P3[26] — General purpose digital input/output pin.
I
STCLK — System tick timer clock input.
O
MAT0[1] — Match output for Timer 0, channel 1.
O
PWM1[3] — Pulse Width Modulator 1, output 3.
P4[0] to P4[31]
I/O
Port 4: Port 4 is a 32-bit I/O port with individual direction controls for each bit. The
operation of port 4 pins depends upon the pin function selected via the pin connect
block. Pins 0 through 27, 30, and 31 of this port are not available.
P4[28]/RX_MCLK/
MAT2[0]/TXD3
82[1]
I/O
P4[28] — General purpose digital input/output pin.
I
RX_MCLK — I2S receive master clock. (LPC1768/66/65 only).
O
MAT2[0] — Match output for Timer 2, channel 0.
O
TXD3 — Transmitter output for UART3.
P4[29]/TX_MCLK/
MAT2[1]/RXD3
85[1]
I/O
P4[29] — General purpose digital input/output pin.
I
TX_MCLK — I2S transmit master clock. (LPC1768/66/65 only).
O
MAT2[1] — Match output for Timer 2, channel 1.
I
RXD3 — Receiver input for UART3.
TDO/SWO
1[1]
O
TDO — Test Data out for JTAG interface.
O
SWO — Serial wire trace output.
TDI
2[1]
I
TDI — Test Data in for JTAG interface.
TMS/SWDIO
3[1]
I
TMS — Test Mode Select for JTAG interface.
I/O
SWDIO — Serial wire debug data input/output.
TRST
4[1]
I
TRST — Test Reset for JTAG interface.
TCK/SWDCLK
5[1]
I
TCK — Test Clock for JTAG interface.
I
SWDCLK — Serial wire clock.
RTCK
100[1]
I/O
RTCK — JTAG interface control signal.
RSTOUT
14
O
RSTOUT — This is a 3.3 V pin. LOW on this pin indicates LPC1768/66/65/64
being in Reset state.
RESET
17[7]
I
External reset input: A LOW on this pin resets the device, causing I/O ports and
peripherals to take on their default states, and processor execution to begin at
address 0. TTL with hysteresis, 5 V tolerant.
XTAL1
22[8]
I
Input to the oscillator circuit and internal clock generator circuits.
XTAL2
23[8]
O
Output from the oscillator amplifier.
RTCX1
16[8]
I
Input to the RTC oscillator circuit.
RTCX2
18[8]
O
Output from the RTC oscillator circuit.
VSS
31, 41,
55, 72,
97, 83[8]
I
ground: 0 V reference.
VSSA
11[8]
I
analog ground: 0 V reference. This should nominally be the same voltage as VSS,
but should be isolated to minimize noise and error.
VDD(3V3)
28, 54,
71, 96[8]
I
3.3 V supply voltage: This is the power supply voltage for the I/O ports.
VDD(REG)(3V3)
42, 84[8]
I
3.3 V voltage regulator supply voltage: This is the supply voltage for the on-chip
voltage regulator only.
Table 3.
Pin description …continued
Symbol
Pin
Type
Description



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