SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163

SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163

SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS

SDAS276 – DECEMBER 1994

6

POST OFFICE BOX 655303

typical clear, preset, count, and inhibit sequences

′ALS161B, ′AS161, ′ALS163B, and ′AS163

The following sequence is illustrated below:

1.

Clear outputs to zero (

′ALS161B and ′AS161 are asynchronous; ′ALS163B and ′AS163 are

synchronous.)

2.

Preset to binary 12

3.

Count to 13, 14, 15, 0, 1, and 2

4.

Inhibit

Data

Inputs

Data

Outputs

CLR

LOAD

A

B

C

D

CLK

ENP

ENT

RCO

QA

QB

QC

QD

Async

Clear

Sync

Clear

Preset

Count

Inhibit

12

13

14

15

0

1

2