Datasheet

ZADCS1282/1242/1222 Family

Copyright © 2008, ZMD AG, Rev. 1.1

All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The

Information furnished in this publication is preliminary and subject to changes without notice.

12/21

Single-ended or differential

nCS

1

DIN

2

DGND

3

AGND

4

5

COM

6

CH0

7

CH1

8

CH4

9

CH5

10

SCLK 20

SSTRB 19

DOUT 18

nSHDN 17

VDD 16

n.c. 15

CH2 14

CH3 13

CH6 12

CH7 11

ZADCS1282

≥ 4.7µF

0.1µF

10µF

µC

+2.7V to 5.25V

Single-ended or differential

analog inputs, 0V … +2.5V

nCS

1

DIN

2

DGND

3

AGND

4

5

COM

6

CH0

7

CH1

8

CH4

9

CH5

10

SCLK 20

SSTRB 19

DOUT 18

nSHDN 17

VDD 16

CH2 14

CH3 13

CH6 12

CH7 11

ZADCS1282V

47nF

≥ 4.7µF

0.1µF

10µF

µC

+2.7V to 5.25V

Figure 4: Basic application schematic for ZADCS1282V

Table 5: Channel selection in Single Ended Mode

(SGL/DIF = HIGH)

A2 A1 A0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM

0

0

0

IN+

IN-

1

0

0

IN+

IN-

0

0

1

IN+

IN-

1

0

1

IN+

IN-

0

1

0

IN+

IN-

1

1

0

IN+

IN-

0

1

1

IN+

IN-

1

1

1

IN+

IN-

Table 6: Channel selection in Differential Mode

(SGL/DIF = LOW)

A2 A1 A0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7

0

0

0

IN+

IN-

0

0

1

IN+

IN-

0

1

0

IN+

IN-

0

1

1

IN+

IN-

1

0

0

IN-

IN+

1

0

1

IN-

IN+

1

1

0

IN-

IN+

1

1

1

IN-

IN+

2 DETAILED DESCRIPTION

2.1

General Operation

The ZADCS12x2 family is a set of classic successive

approximation register (SAR) type converters. The archi-

tecture is based on a capacitive charge redistribution

DAC merged with a resistor string DAC building a hybrid

converter with excellent monotonicity and DNL properties.

The Sample & Hold function is inherent to the capacitive

DAC. This avoids additional active components in the

signal path that could distort the input signal or introduce

errors.

All devices in the ZADCS12x2 family build on the same

converter core and differ only in the number of input

channels and the availability of an internal reference

voltage generator. The ZADCS12x2V versions are

equipped with a highly accurate internal 1.25V bandgap

reference which is available at the VREFADJ pin. The

bandgap voltage is further amplified by an internal buffer

amplifier to 2.50V that is available at pin VREF. All other

versions come without the internal reference and the

internal buffer amplifier. They require an external refer-

ence supplied at VREF, with the benefit of considerably

lower power consumption.

A basic application schematic for ZADC1282V is shown

can also be operated with an external reference, if

VREFADJ is tied to VDD.

2.2

Analog Input

The analog input to the converter is fully differential. Both

diagram at front page) get sampled during the acquisition

period enabling the converter to be used in fully differen-

tial applications where both signals can vary over time.

The ZADCS12x2 family converters do not require that the

negative input signal be kept constant within ± 0.5LSB

during the entire conversion as is commonly required by

converters featuring pseudo differential operation only.

The input signals can be applied single ended, refer-

enced to the COM pin, or differential, using pairs of the

input channels. The desired configuration is selectable for

every conversion via the Control-Byte received on DIN

pin of the digital interface (see further description below)

A block diagram of the input multiplexer is shown in

Control-Byte bits A2, A1, A0 and SGL/DIF to the configu-

ration of the analog multiplexer. The entire table applies

only to ZADCS1282 devices. For ZADCS1242 devices bit

A1 is don’t care, for ZADCS1222 devices A1 and A0 are

don’t care.

swing between –0.2V and VDD+0.2V. However, depend-

ing on the selected conversion mode – uniploar or bipo-

lar – certain input voltage relations can limit the output

code range of the converter.

Figure 5: Basic application schematic for ZADCS1282