SN54ALS299, SN74ALS299

8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS

WITH 3-STATE OUTPUTS

SDAS220B – DECEMBER 1982 – REVISED DECEMBER 1994

2

POST OFFICE BOX 655303

FUNCTION TABLE

MODE

INPUTS

I/O PORTS

OUTPUTS

MODE

CLR

S1

S0

OE1†

OE2†

CLK

SL

SR

A/QA B/QB C/QC D/QD E/QE

F/QF G/QG H/QH

QA

′

QH

′

Clear

L

L

L

X

L

H

L

X

H

L

L

X

L

L

X

X

X

X

X

X

X

X

X

X

L

L

X

L

L

X

L

L

X

L

L

X

L

L

X

L

L

X

L

L

X

L

L

X

L

L

L

L

L

L

Hold

H

H

L

X

L

X

L

L

L

L

X

L

X

X

X

X

QA0

QA0

QB0

QB0

QC0

QC0

QD0

QD0

QE0

QE0

QF0

QF0

QG0

QG0

QH0

QH0

QA0

QA0

QH0

QH0

Shift

Right

H

H

L

L

H

H

L

L

L

L

↑

↑

X

X

H

L

H

L

QAn

QAn

QBn

QBn

QCn

QCn

QDn

QDn

QEn

QEn

QFn

QFn

QGn

QGn

H

L

QGn

QGn

Shift

Left

H

H

H

H

L

L

L

L

L

L

↑

↑

H

L

X

X

QBn

QBn

QCn

QCn

QDn

QDn

QEn

QEn

QFn

QFn

QGn

QGn

QHn

QHn

H

L

QBn

QBn

H

L

Load

H

H

H

X

X

↑

X

X

a

b

c

d

e

f

g

h

a

h

NOTE: a ...h = the level of the steady-state input at inputs A through H, respectively. This data is loaded into the flip-flops while the flip-flop outputs

are isolated from the I/O terminals.

† When one or both output-enable inputs are high, the eight I/O terminals are disabled to the high-impedance state; however, sequential operation

or clearing of the register is not affected.

SRG8

M

0

3

R

9

6

14

5

15

4

8

2

3

0

1

S0

1

19

S1

12

CLK

5, 13

1,4D

11

SR

3,4D

7

6, 13

3,4D

13

17

12, 13

2,4D

18

SL

3,4D

16

&

3EN13

C4/1

→/2←

QA

′

QH

′

CLR

OE1

OE2

A/QA

H/QH

B/QB

C/QC

D/QD

E/QE

F/QF

G/QG

Z5

Z6

Z12

‡ This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.