SN54HC148, SN74HC148

8LINE TO 3LINE PRIORITY ENCODERS

SCLS109G − MARCH 1984 − REVISED APRIL 2004

7

POST OFFICE BOX 655303

APPLICATION INFORMATION

0 1

23

4

5

67 EI

EO A0

A1

A2 GS

’HC148

0 1

23

4

5

67 EI

EO

A0

A1

A2

GS

’HC148

’HC08

0 1

2 3

4

5

6 7

8 9 10 11 12 13 14 15

Enable

(active low)

01

2

3

Encoded Data (active low)

Priority Flag

(active low)

16-Line Data (active low)

0 1

23

4

5

67 EI

EO A0

A1

A2 GS

’HC148

0 1

23

4

5

67 EI

EO

A0

A1

A2

GS

’HC148

’HC00

0 1

2 3

4

5

6 7

8 9 10 11 12 13 14 15

Enable

(active low)

01

2

3

Encoded Data (active high)

Priority Flag

(active high)

16-Line Data (active low)

Figure 2. Priority Encoder for 16 Bits

Because the ’HC148 devices are combinational logic circuits, wrong addresses can appear during input transients.

Moreover, a change from high to low at EI can cause a transient low on GS when all inputs are high. This must be

considered when strobing the outputs.