SN54HC193, SN74HC193

4BIT SYNCHRONOUS UP/DOWN COUNTERS

(DUAL CLOCK WITH CLEAR)

SCLS122D − DECEMBER 1982 − REVISED OCTOBER 2003

2

POST OFFICE BOX 655303

description/ordering information (continued)

The outputs of the four flip-flops are triggered on a low-to-high-level transition of either count (clock) input (UP

or DOWN). The direction of counting is determined by which count input is pulsed while the other count input

is high.

All four counters are fully programmable; that is, each output may be preset to either level by placing a low on

the load (LOAD) input and entering the desired data at the data inputs. The output changes to agree with the

data inputs independently of the count pulses. This feature allows the counters to be used as modulo-N dividers

simply by modifying the count length with the preset inputs.

A clear (CLR) input has been provided that forces all outputs to the low level when a high level is applied. The

clear function is independent of the count and LOAD inputs.

These counters were designed to be cascaded without the need for external circuitry. The borrow (BO) output

produces a low-level pulse while the count is zero (all outputs low) and DOWN is low. Similarly, the carry (CO)

output produces a low-level pulse while the count is maximum (9 or 15), and UP is low. The counters then can

be cascaded easily by feeding BO and CO to DOWN and UP, respectively, of the succeeding counter.