SN54HC594, SN74HC594

8-BIT SHIFT REGISTERS

WITH OUTPUT REGISTERS

SCLS040C – DECEMBER 1982 – REVISED FEBRUARY 1998

6

POST OFFICE BOX 655303

timing requirements over recommended operating free-air temperature range (unless otherwise

noted)

VCC

TA = 25°C

SN54HC594

SN74HC594

UNIT

VCC

MIN

MAX

MIN

MAX

MIN

MAX

UNIT

2 V

5

3.3

4

fclock

Clock frequency

4.5 V

25

17

20

MHz

6 V

29

20

24

2 V

100

150

125

SRCLK or RCLK high or low

4.5 V

20

30

25

t

Pulse duration

6 V

17

25

21

ns

tw

Pulse duration

2 V

100

150

125

ns

SRCLR or RCLR low

4.5 V

20

30

25

6 V

17

25

21

↑

2 V

90

135

110

SER before SRCLK

↑

4.5 V

18

27

22

6 V

15

23

19

↑

↑†

2 V

90

135

110

SRCLK

↑ before RCLK↑†

4.5 V

18

27

22

6 V

15

23

19

↑

2 V

50

75

63

tsu

Setup time

SRCLR low before RCLK

↑

4.5 V

10

15

13

ns

6 V

9

13

11

↑

2 V

20

20

20

SRCLR high (inactive) before SRCLK

↑

4.5 V

10

10

10

6 V

10

10

10

↑

2 V

5

5

5

RCLR high (inactive) before SRCLK

↑

4.5 V

5

5

5

6 V

5

5

5

↑

2 V

5

5

5

th

Hold time, SER after SRCLK

↑

4.5 V

5

5

5

ns

6 V

5

5

5

† This setup time ensures the output register sees stable data from the shift-register outputs. The clocks may be tied together, in which case the

output register is one clock pulse behind the shift register.

PRODUCT PREVIEW information concerns products in the formative or

design phase of development. Characteristic data and other

specifications are design goals. Texas Instruments reserves the right to

change or discontinue these products without notice.