SN74ACT3622

256

× 36 × 2

CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SCAS247D – AUGUST 1993 – REVISED APRIL 1998

6

POST OFFICE BOX 655303

Terminal Functions (continued)

TERMINAL

NAME

I/O

DESCRIPTION

ORB

O

(port B)

Output-ready flag. ORB is synchronized to the low-to-high transition of CLKB. When ORB is low, FIFO1 is empty and

reads from its memory are disabled. Ready data is present on the output register of FIFO1 when ORB is high. ORB

is forced low when FIFO1 is reset and goes high on the third low-to-high transition of CLKB after a word is loaded to

empty memory.

RST1

I

FIFO1 reset. To reset FIFO1, four low-to-high transitions of CLKA and four low-to-high transitions of CLKB must occur

while RST1 is low. The low-to-high transition of RST1 latches the status of FS0 and FS1 for AFA and AEB offset

selection. FIFO1 must be reset upon power up before data is written to its RAM.

RST2

I

FIFO2 reset. To reset FIFO2, four low-to-high transitions of CLKA and four low-to-high transitions of CLKB must occur

while RST2 is low. The low-to-high transition of RST2 latches the status of FS0 and FS1 for AFB and AEA offset

selection. FIFO2 must be reset upon power up before data is written to its RAM.

W/RA

I

Port-A write/read select. A high on W/RA selects a write operation and a low selects a read operation on port A for a

low-to-high transition of CLKA. The A0 – A35 outputs are in the high-impedance state when W/RA is high.

W/RB

I

Port-B write/read select. A low on W/RB selects a write operation and a high selects a read operation on port B for a

low-to-high transition of CLKB. The B0 – B35 outputs are in the high-impedance state when W/RB is low.

detailed description

reset

The FIFO memories of the SN74ACT3622 are reset separately by taking their reset (RST1, RST2) inputs low

for at least four port-A clock (CLKA) and four port-B clock (CLKB) low-to-high transitions. The reset inputs can

switch asynchronously to the clocks. A FIFO reset initializes the internal read and write pointers and forces the

input-ready (IRA, IRB) flag low, the output-ready (ORA, ORB) flag low, the almost-empty (AEA, AEB) flag low,

and the almost-full (AFA, AFB) flag high. Resetting a FIFO also forces the mailbox (MBF1, MBF2) flag of the

parallel mailbox register high. After a FIFO is reset, its IR flag is set high after two clock cycles to begin normal

operation. A FIFO must be reset after power up before data is written to its memory.

A low-to-high transition on a FIFO reset (RST1, RST2) input latches the value of the flag-select (FS0, FS1)

inputs for choosing the almost-full and almost-empty offset programming method (see

almost-empty flag and

almost-full flag offset programming).

almost-empty flag and almost-full flag offset programming

Four registers in the SN74ACT3622 are used to hold the offset values for the AE and AF flags. The port-B

almost-empty (AEB) flag offset register is labeled X1 and the port-A almost-empty (AEA) flag offset register is

labeled X2. The port-A almost-full (AFA) flag offset register is labeled Y1 and the port-B almost-full (AFB) flag

offset register is labeled Y2. The index of each register name corresponds to its FIFO number. The offset

registers can be loaded with preset values during the reset of a FIFO or they can be programmed from port A

(see Table 1).