SN74ACT3622

256

× 36 × 2

CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SCAS247D – AUGUST 1993 – REVISED APRIL 1998

16

POST OFFICE BOX 655303

tsu(EN)

CLKB

ORA

W1

B0 – B35

MBB

ENB

CSB

W/RB

IRB

CLKA

CSA

W/RA

MBA

ENA

W1

A0 – A35

tc

th(EN)

tsu(EN)

th(EN)

tpd(C-OR)

tpd(C-OR)

Old Data in FIFO2 Output Register

Old Data in FIFO2 Output Register

ta

12

3

Low

High

th(EN)

tsu(EN)

th(D)

tsu(D)

tsk1†

tc

Low

Low

Low

Low

tw(CLKL)

tw(CLKH)

tw(CLKL)

tw(CLKH)

† tsk1 is the minimum time between a rising CLKB edge and a rising CLKA edge for ORA to transition high and to clock the next word to the

FIFO2 output register in three CLKA cycles. If the time between the rising CLKB edge and rising CLKA edge is less than tsk1, the transition

of ORA high and load of the first word to the output register may occur one CLKA cycle later than shown.

Figure 8. ORA-Flag Timing and First Data-Word Fall Through When FIFO2 Is Empty