SN74ACT3632

512

× 36 × 2

CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY

SCAS224D – JUNE 1992 – REVISED APRIL 1998

3

POST OFFICE BOX 655303

description

The SN74ACT3632 is a high-speed, low-power CMOS clocked bidirectional FIFO memory. It supports clock

frequencies up to 67 MHz and has read access times as fast as 11 ns. Two independent 512

× 36 dual-port

SRAM FIFOs on the chip buffer data in opposite directions. Each FIFO has flags to indicate empty and full

conditions and two programmable flags, almost full (AF) and almost empty (AE) to indicate when a selected

number of words is stored in memory. Communication between each port can bypass the FIFOs via two 36-bit

mailbox registers. Each mailbox register has a flag to signal when new mail has been stored. Two or more

devices can be used in parallel to create wider datapaths.

The SN74ACT3632 is a clocked FIFO, which means each port employs a synchronous interface. All data

transfers through a port are gated to the low-to-high transition of a port clock by enable signals. The clocks for

each port are independent of one another and can be asynchronous or coincident. The enables for each port

are arranged to provide a simple bidirectional interface between microprocessors and/or buses with

synchronous control.

The input-ready (IRA, IRB) flag and almost-full (AFA, AFB) flag of a FIFO are two-stage synchronized to the

port clock that writes data to its array. The output-ready (ORA, ORB) flag and almost-empty (AEA, AEB) flag

of a FIFO are two-stage synchronized to the port clock that reads data from its array. Offset values for the AF

and AE flags of both FIFOs can be programmed from port A.

The SN74ACT3632 is characterized for operation from 0

°C to 70°C.

For more information on this device family, see the following application reports:

(literature number SCAA007)

SCAA005)