SN74ACT3651

2048

× 36

CLOCKED FIRST-IN, FIRST-OUT MEMORY

SCAS439D – JUNE 1994 – REVISED FEBRUARY 1999

22

POST OFFICE BOX 655303

timing requirements over recommended ranges of supply voltage and operating free-air

temperature (see Figures 1 through 16)

’ACT3651-15

’ACT3651-20

’ACT3651-30

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

UNIT

fclock

Clock frequency, CLKA or CLKB

66.7

50

33.4

MHz

tc

Clock cycle time, CLKA or CLKB

15

20

30

ns

tw(CH)

Pulse duration, CLKA and CLKB high

6

8

12

ns

tw(CL)

Pulse duration, CLKA and CLKB low

6

8

12

ns

tsu(D)

Setup time, A0 – A35 before CLKA

↑ and B0–B35 before CLKB↑

4

5

6

ns

tsu(EN)

Setup time, CSA, W/RA, ENA, and MBA before CLKA

↑;

CSB, W/RB, ENB, MBB, RTM, and RFM before CLKB

↑

4

5

6

ns

tsu(RS)

Setup time, RST low before CLKA

↑ or CLKB↑†

5

6

7

ns

tsu(FS)

Setup time, FS0 and FS1 before RST high

12

13

14

ns

tsu(SD)‡

Setup time, FS0/SD before CLKA

↑

4

5

6

ns

tsu(SEN)‡

Setup time, FS1/SEN before CLKA

↑

5

6

7

ns

th(D)

Hold time, A0 – A35 after CLKA

↑ and B0–B35 after CLKB↑

1

1

1

ns

th(EN)

Hold time, CSA, W/RA, ENA, and MBA after CLKA

↑;

CSB, W/RB, ENB, RFM, and MBB after CLKB

↑

0

0

0

ns

th(RS)

Hold time, RST low after CLKA

↑ or CLKB↑†

5

6

7

ns

th(FS)

Hold time, FS0 and FS1 after RST high

2

3

3

ns

th(SP)‡

Hold time, FS1/SEN high after RST high

1

1

1

ns

th(SD)‡

Hold time, FS0/SD after CLKA

↑

0

0

0

ns

th(SEN)‡

Hold time, FS1/SEN after CLKA

↑

0

0

0

ns

tsk(1)§

Skew time between CLKA

↑ and CLKB↑ for OR and IR

6

8

10

ns

tsk(2)§

Skew time between CLKA

↑ and CLKB↑ for AE and AF

12

16

20

ns

† Requirement to count the clock edge as one of at least four needed to reset a FIFO

‡ Applies only when serial load method is used to program flag offset registers

§ Skew time is not a timing constraint for proper device operation and is included only to illustrate the timing relationship between CLKA cycle and

CLKB cycle.