LTC2230UP datasheet(5/32 Pages) LINER

5 / 32 page

LTC2230/LTC2231

22301fb

POWER REQUIRE E TS

TI I G CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature

range, otherwise specifications are at TA = 25

°C. (Note 4)

The

● denotes the specifications which apply over the full operating temperature

range, otherwise specifications are at TA = 25°C. (Note 9)

LTC2230

LTC2231

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

MIN

TYP

MAX

UNITS

VDD

Analog Supply Voltage

(Note 8)

●

3.1

3.3

3.5

3.1

3.3

3.5

PSHDN

Shutdown Power

SHDN = H, OE = H, No CLK

PNAP

Nap Mode Power

SHDN = H, OE = L, No CLK

LVDS OUTPUT MODE

OVDD

Output Supply Voltage

(Note 8)

●

3.3

3.6

3.3

3.6

IVDD

Analog Supply Current

●

264

288

196

212

IOVDD

Output Supply Current

●

PDISS

Power Dissipation

●

1045

1175

822

924

CMOS OUTPUT MODE

OVDD

Output Supply Voltage

(Note 8)

●

0.5

3.3

3.6

0.5

3.3

3.6

IVDD

Analog Supply Current

●

264

288

196

212

PDISS

Power Dissipation

890

660

LTC2230

LTC2231

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

MIN

TYP

MAX

UNITS

Sampling Frequency

(Note 8)

●

170

135

MHz

ENC Low Time (Note 7)

Duty Cycle Stabilizer Off

●

2.8

2.94

500

3.5

3.7

500

Duty Cycle Stabilizer On

●

2.94

500

3.7

500

ENC High Time (Note 7)

Duty Cycle Stabilizer Off

●

2.8

2.94

500

3.5

3.7

500

Duty Cycle Stabilizer On

●

2.94

500

3.7

500

tAP

Sample-and-Hold Aperture Delay

tOE

Output Enable Delay

(Note 7)

●

510

LVDS OUTPUT MODE

ENC to DATA Delay

(Note 7)

●

1.3

2.2

3.5

1.3

2.2

3.5

ENC to CLOCKOUT Delay

(Note 7)

●

1.3

2.2

3.5

1.3

2.2

3.5

DATA to CLOCKOUT Skew

(tC - tD) (Note 7)

●

–0.6

0.6

–0.6

0.6

Rise Time

0.5

Fall Time

0.5

Pipeline Latency

Cycles

CMOS OUTPUT MODE

ENC to DATA Delay

(Note 7)

●

1.3

2.1

3.5

1.3

2.1

3.5

ENC to CLOCKOUT Delay

(Note 7)

●

1.3

2.1

3.5

1.3

2.1

3.5

DATA to CLOCKOUT Skew

(tC - tD) (Note 7)

●

–0.6

0.6

–0.6

0.6

Pipeline Latency Full Rate CMOS

Cycles

Demuxed Interleaved

Cycles

Demuxed Simultaneous

5 and 6

Cycles

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