SN74F161A

SYNCHRONOUS 4-BIT BINARY COUNTER

SDFS056A – D2932, MARCH 1987 – REVISED OCTOBER 1993

2–7

POST OFFICE BOX 655303

timing requirements over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted)

VCC = 5 V,

TA = 25°C

MIN

MAX

UNIT

MIN

MAX

fclock

Clock frequency

0

100

0

90

MHz

CLK high or low (loading)

5

5

t

Pulse duration

CLK (counting)

High

4

4

ns

tw

Pulse duration

CLK (counting)

Low

6

7

ns

CLR low

5

5

Data before CLK

↑

High or low

5

5

LOAD before CLK

↑

High

11

11.5

tsu

Setup time

LOAD before CLK

↑

Low

8.5

9.5

ns

ENP and ENT before CLK

↑

High

11

11.5

ENP and ENT before CLK

↑

Low

5

5

Data after CLK

↑

High or low

2

2

th

Hold time

LOAD after CLK

↑

High

2

2

ns

th

Hold time

LOAD after CLK

↑

Low

0

0

ns

ENP and ENT after CLK

↑

High or low

0

0

tsu

Inactive-state setup time, CLR high before CLK

↑†

6

6

ns

† Inactive-state state setup time is also referred to as recovery time.

switching characteristics (see Note 2)

PARAMETER

FROM

(INPUT)

TO

(OUTPUT)

VCC = 5 V,

CL = 50 pF,

RL = 500 Ω,

TA = 25°C

VCC = 4.5 V to 5.5 V,

CL = 50 pF,

RL = 500 Ω,

TA = MIN to MAX‡

UNIT

MIN

TYP

MAX

MIN

MAX

fmax

100

120

90

MHz

tPLH

CLK (LOAD high)

Any Q

2.7

5.1

7.5

2.7

8.5

ns

tPHL

CLK (LOAD high)

Any Q

2.7

7.1

10

2.7

11

ns

tPLH

CLK (LOAD low)

Any Q

3.2

5.6

8.5

3.2

9.5

ns

tPHL

CLK (LOAD low)

Any Q

3.2

5.6

8.5

3.2

9.5

ns

tPLH

CLK

RCO

4.2

9.6

14

4.2

15

ns

tPHL

CLK

RCO

4.2

9.6

14

4.2

15

ns

tPLH

ENT

RCO

1.7

4.1

7.5

1.7

8.5

ns

tPHL

ENT

RCO

1.7

4.1

7.5

1.7

8.5

ns

tPHL

CLR

Any Q

4.7

8.6

12

4.7

13

ns

tPHL

CLR

RCO

3.7

7.6

10.5

3.7

11.5

ns

‡ For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.

NOTE 2: Load circuits and waveforms are shown in Section 1.