SN74S1051

12-BIT SCHOTTKY BARRIER DIODE

BUS-TERMINATION ARRAY

SDLS018B – SEPTEMBER 1990 – REVISED MARCH 2003

1

POST OFFICE BOX 655303

Bus-Oriented Systems

description/ordering information

This Schottky barrier diode bus-termination array

is designed to reduce reflection noise on memory

bus lines. This device consists of a 12-bit

high-speed Schottky diode array suitable for

ORDERING INFORMATION

TA

PACKAGE†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

PDIP – N

Tube

SN74S1051N

SN74S1051N

SOIC

D

Tube

SN74S1051D

S1051

0

°C to 70°C

SOIC – D

Tape and reel

SN74S1051DR

S1051

SOP – NS

Tape and reel

SN74S1051NSR

74S1051

TSSOP – PW

Tape and reel

SN74S1051PWR

S1051

† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are

available at www.ti.com/sc/package.

schematic diagrams

D01

2

D02

3

D03

4

D04

5

D05

6

D06

7

D07

10

D08

11

D09

12

D10

13

D11

14

D12

15

8

GND

9

GND

VCC

1

VCC

16

Copyright

 2003, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

D, N, NS, OR PW PACKAGE

(TOP VIEW)

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

D01

D02

D03

D04

D05

D06

GND

D12

D11

D10

D09

D08

D07

GND