SN75185

MULTIPLE RS-232 DRIVERS AND RECEIVERS

SLLS181A – DECEMBER 1994 – REVISED NOVEMBER 1998

4

POST OFFICE BOX 655303

supply currents

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

VDD = 9 V,

VSS = – 9 V

15

All inputs at 1.9 V,

No load

VDD = 12 V,

VSS = – 12 V

19

mA

IDD

Supply current from VDD

VDD = 15 V,

VSS = – 15 V

25

IDD

Supply current from VDD

VDD = 9 V,

VSS = – 9 V

4.5

All inputs at 0.8 V,

No load

VDD = 12 V,

VSS = – 12 V

5.5

mA

VDD = 15 V,

VSS = – 15 V

9

VDD = 9 V,

VSS = – 9 V

–15

All inputs at 1.9 V,

No load

VDD = 12 V,

VSS = – 12 V

–19

mA

ISS

Supply current from VSS

VDD = 15 V,

VSS = – 15 V

–25

ISS

Supply current from VSS

VDD = 9 V,

VSS = – 9 V

– 3.2

All inputs at 0.8 V,

No load

VDD = 12 V,

VSS = – 12 V

– 3.2

mA

VDD = 15 V,

VSS = – 15 V

– 3.2

ICC

Supply current from VCC

VCC = 5 V,

All inputs at 5 V,

No load

30

mA

DRIVER SECTION

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VOH

High-level output voltage

VIL = 0.8 V,

RL = 3 kΩ,

See Figure 1

6

7.5

V

VOL

Low-level output voltage (see Note 6)

VIH = 1.9 V,

RL = 3 kΩ,

See Figure 1

– 7.5

–6

V

IIH

High-level input current

VI = 5 V,

See Figure 2

10

µA

IIL

Low-level input current

VI = 0,

See Figure 2

– 1.6

mA

IOS(H)

High-level short-circuit output current

(see Note 7)

VIL = 0.8 V,

VO = 0,

See Figure 1

– 4.5

–12

– 19.5

mA

IOS(L)

Low-level short-circuit output current

VIH = 2 V,

VO = 0,

See Figure 1

4.5

12

19.5

mA

ro

Output resistance (see Note 8)

VCC = VDD = VSS = 0,

VO = – 2 V to 2 V

300

Ω

NOTES:

6. The algebraic convention, where the more positive (less negative) limit is designated as maximum, is used in this data sheet for logic

levels only (e.g., if –10 V is maximum, the typical value is a more negative voltage).

7. Output short-circuit conditions must maintain the total power dissipation below absolute maximum ratings.

8. Test conditions are those specified by TIA/EIA-232-F and as listed above.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

tPLH

Propagation delay time, low-to-high-level output

RL = 3 kΩ to 7 kΩ, CL = 15 pF,

315

500

ns

tPHL

Propagation delay time, high-to-low-level output

L

,

L

,

See Figure 3

75

175

ns

tTLH

Transition time low to high level output

RL = 3 kΩ to 7 kΩ, CL = 15 pF,

See Figure 3

60

100

ns

tTLH

Transition time, low-to-high-level output

RL = 3 kΩ to 7 kΩ, CL = 2500 pF,

See Figure 3 and Note 9

1.7

2.5

µs

tTHL

Transition time high to low level output

RL = 3 kΩ to 7 kΩ, CL = 15 pF,

See Figure 3

40

75

ns

tTHL

Transition time, high-to-low-level output

RL = 3 kΩ to 7 kΩ, CL = 2500 pF,

See Figure 3 and Note 10

1.5

2.5

µs

NOTES:

9. Measured between – 3-V and 3-V points of the output waveform (TIA/EIA-232-F conditions), all unused inputs are tied.

10. Measured between 3-V and – 3-V points of the output waveform (TIA/EIA-232-F conditions), all unused inputs are tied.