SN75207B

DUAL SENSE AMPLIFIER FOR MOS MEMORIES

OR DUAL HIGH-SENSITIVITY LINE RECEIVERS

SLLS096C – JULY 1973 – REVISED MARCH 1997

2

POST OFFICE BOX 655303

2G

2B

2A

1G

1B

1A

S

8

11

12

5

2

1

6

EN

9

2Y

1Y

4

&

† This symbol is in accordance with ANSI/IEEE Std 91-1984

and IEC Publication 617-12.

logic diagram (positive logic)

1Y

4

2Y

9

11

2B

12

2A

8

2G

5

1G

2

1B

1A

S

1

6

schematic (each receiver)

4 k

Ω

4.25 k

Ω

6

5, 8

GND

7

4, 9

3 k

Ω

3 k

Ω

800

Ω

1 k

Ω

760

Ω

4.8 k

Ω

120

Ω

1.6 k

Ω

400

Ω

1 k

Ω

1 k

Ω

13

VCC –

2, 11

B

Inputs

A

1, 12

14

VCC +

To Other Receiver

Y

G

S

Resistor values shown are nominal.

Common

To Both

Receivers