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75C1406 Datasheet(PDF) 1 Page - Texas Instruments |
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75C1406 Datasheet(HTML) 1 Page - Texas Instruments |
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1 / 8 page ![]() SN75C1406 TRIPLE LOW-POWER DRIVERS/RECEIVERS SLLS148D – MAY 1990 – REVISED DECEMBER 1999 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 D Meet or Exceed the Requirements of TIA/EIA-232-F and ITU Recommendation V.28 D Very Low Power Consumption . . . 5 mW Typ D Wide Driver Supply Voltage Range . . . ±4.5 V to ±15 V D Driver Output Slew Rate Limited to 30 V/ µs Max D Receiver Input Hysteresis . . . 1000 mV Typ D Push-Pull Receiver Outputs D On-Chip Receiver 1-µs Noise Filter D Functionally Interchangeable With Motorola MC145406 and Texas Instruments TL145406 D Package Options Include Plastic Small-Outline (D, DW, NS) Packages and (N) DIPs description The SN75C1406 is a low-power BiMOS device containing three independent drivers and receivers that are used to interface data terminal equipment (DTE) with data circuit-terminating equipment (DCE). This device is designed to conform to TIA/EIA-232-F. The drivers and receivers of the SN75C1406 are similar to those of the SN75C188 quadruple driver and SN75C189A quadruple receiver, respectively. The drivers have a controlled output slew rate that is limited to a maximum of 30 V/ µs, and the receivers have filters that reject input noise pulses shorter than 1 µs. Both these features eliminate the need for external components. The SN75C1406 is designed using low-power techniques in a BiMOS technology. In most applications, the receivers contained in these devices interface to single inputs of peripheral devices such as ACEs, UARTs, or microprocessors. By using sampling, such peripheral devices are usually insensitive to the transition times of the input signals. If this is not the case, or for other uses, it is recommended that the SN75C1406 receiver outputs be buffered by single Schmitt input gates or single gates of the HCMOS, ALS, or 74F logic families. The SN75C1406 is characterized for operation from 0 °C to 70°C. logic symbol† † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. 1RY 15 2RY 13 3RY 11 1DA 14 2DA 12 3DA 10 1RA 2 2RA 4 3RA 6 1DY 3 2DY 5 3DY 7 logic diagram, each driver and receiver DY RA DA RY Copyright © 1999, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD 1RA 1DY 2RA 2DY 3RA 3DY VSS VCC 1RY 1DA 2RY 2DA 3RY 3DA GND D, DW, N, OR NS PACKAGE (TOP VIEW) |
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