TCM29C23, TCM129C23

VARIABLE-FREQUENCY PCM OR DSP INTERFACE

SCTS029A – AUGUST 1989 –REVISED JULY 1996

13

POST OFFICE BOX 655303

PARAMETER MEASUREMENT INFORMATION

CLKX

FSX Input

(nonsignaling

frames)

CLKX

PCM OUT

TSX Output

tr

tf

Time-Slot 1

12

3

4

5

6

7

8

12

3

4

5

6

7

8

Time-Slot N

tpd1

tpd2

tpd3

tpd5

tpd4

Bit 1†

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

Bit 8†

td(FSX)

td(FSX)

tw(CLK)

tc(CLK)

† Bit 1 = MSB = sign bit and locked in first on PCM IN or clocked out first on PCM OUT. Bit 8 = LSB = least significant bit and is clocked in last

on PCM IN or is clocked out last on PCM OUT.

NOTE A: Inputs are driven from 0.45 V to 2.4 V. Time intervals are referenced to 2 V if the high level is indicated and 0.8 V if the low level is

indicated.

Figure 3. Transmit Timing (Fixed-Data Rate)

CLKR

FSR Input

(nonsignaling

frames)

CLK

PCM IN

Time-Slot 1

12

3

4

5

6

7

8

td(FSR)

td(FSR) tr

tf

tw(CLK)

tc(CLK)

12

3

4

5

6

7

8

Time-Slot N

tsu(PCM IN)

th(PCM IN)

Bit 1†

Valid

Bit 2

Valid

Bit 3

Valid

Bit 4

Valid

Bit 5

Valid

Bit 6

Valid

Bit 7

Valid

Bit 8†

Valid

† Bit 1 = MSB = sign bit and locked in first on PCM IN or clocked out first on PCM OUT. Bit 8 = LSB = least significant bit and is clocked in last

on PCM IN or is clocked out last on PCM OUT.

NOTE A: Inputs are driven from 0.45 V to 2.4 V. Time intervals are referenced to 2 V if the high level is indicated and 0.8 V if the low level is

indicated.

Figure 4. Receive Timing (Fixed-Data Rate)