THS1050

10-BIT 50 MSPS IF SAMPLING COMMUNICATIONS

ANALOG-TO-DIGITAL CONVERTER

SLAS278 – APRIL 2000

15

POST OFFICE BOX 655303

APPLICATION INFORMATION

CLK+

VCM

THS1050

CLK–

Impedance Ratio = 1:4

3 V p-p

to

5 V p-p

0.01

µF

0.1

µF

T4-1H

Zo

R = 4 Zo

0.1

µF

R = Zo

ac Signal Source

Figure 20. Driving the Clock From an Impedance Matched Source

The clock signals, CLK+ and CLK–, should be well matched and must both be driven.

A transformer ensures minimal skew between the two complementary channels. However, skew levels of up

to 500 ps between CLK+ and CLK– can be tolerated with some performance degradation.

The clock input can also be driven differentially with a 5 V TTL signal by using an RF transformer to convert the

TTL signal to a differential signal. The TTL signal is ac-coupled to the positive primary terminal with a high pass

circuit. The negative terminal of the transformer is connected to ground (see Figure 21). The transformer

secondary is connected to the CLK inputs.

CLK+

CLK–

VCM

THS1050

0.01

µF

0.1

µF

5 V TTL CLK

0.1

µF

Impedance Ratio = 1:4

T4 - 1H

Figure 21. TTL Clock Input