TL441

LOGARITHMIC AMPLIFIER

SLVS328 – OCTOBER 2000

2

POST OFFICE BOX 655303

functional logic diagram (one half)

–15 dB

–15 dB

Log

Log

Log

Log

Σ

Y (Z)

Y (Z)

A1

(B1)

CA2

(CB2)

CA2

′

(CB2

′)

A2

(B2)

Y

∝ log A1 + log A2; Z ∝ log B1 + log B2 where: A1, A2, B1, and B2 are in dBV, 0 dBV = 1 V.

CA2, CA2

′, CB2, and CB2′ are detector compensation inputs.

schematic

VCC +

Y

Y

A2

A1

CA2

′

CA2

VCC –

8

6

5

7

4

3

1

2

10

11

9

12

13

14

15

Z

Z

B2

B1

GND

CB2

′

CB2