TLC1542C, TLC1542I, TLC1542M, TLC1542Q, TLC1543C, TLC1543I, TLC1543Q

10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH

SERIAL CONTROL AND 11 ANALOG INPUTS

SLAS052E – MARCH 1992 – OCTOBER 1998

13

POST OFFICE BOX 655303

PARAMETER MEASUREMENT INFORMATION

timing diagrams

Access Cycle B

Shift in New Multiplexer Address;

Simultaneously Shift Out Previous

Conversion Value

Sample Cycle B

A/D Conversion

Interval

Initialize

Initialize

MSB

LSB

Previous Conversion Data

MSB

LSB

B3

B2

B1

B0

C3

B9

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

Hi-Z State

1

2

34

56

7

8

9

10

1

I/O

CLOCK

DATA

OUT

ADDRESS

CS

(see Note A)

EOC

NOTE A: To minimize errors caused by noise at CS, the internal circuitry waits for a setup time plus two falling edges of the internal system clock

after CS

↓ before responding to control input signals. Therefore, no attempt should be made to clock in an address until the minimum

CS setup time has elapsed.

Figure 9. Timing for 10-Clock Transfer Using CS