TLC2933IPWR datasheet(19/21 Pages) TI

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TLC2933

HIGH-PERFORMANCE PHASE-LOCKED LOOP

SLAS136A – APRIL 1996 – REVISED JUNE 1997

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

APPLICATION INFORMATION

Phase

Comparator

AGND

DGND

REF IN

DVDD

AVDD

VDD

LOGIC VDD (Digital)

LOGIC GND (Digital)

TEST

FIN – A

VCO INHIBIT

PFD INHIBIT

VCO GND

VCO IN

BIAS

VCO VDD

VCO

R1†

Divide

0.22

µF

FIN – B

† RBIAS resistor

VCO OUT

PFD OUT

Figure 20. Evaluation and Operation Schematic

PCB layout considerations

The TLC2933 contains a high frequency oscillator; therefore, very careful breadboarding and PCB layout is

required for evaluation.

The following design recommendations benefit the TLC2933 user:

D External analog and digital circuitry should be physically separated and shielded as much as possible to

reduce system noise.

D Radio frequency (RF) breadboarding or RF PCB techniques should be used throughout the evaluation and

production process.

D Wide ground leads or a ground plane should be used on the PCB layouts to minimize parasitic inductance

and resistance. The ground plane is the better choice for noise reduction.

D LOGIC VDD and VCO VDD should be separate PCB traces and connected to the best filtered supply point

available in the system to minimize supply cross-coupling.

D VCOVDD to ground and LOGIC VDD to ground should be decoupled with a 0.1-µF capacitor placed as close

as possible to the appropriate device terminals.

D The no-connection (NC) terminal on the package should be connected to ground to prevent stray pickup.

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