TLC320AD50C datasheet(21/53 Pages) TI

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2–5

Figure 2–6 is a timing diagram of this procedure.

DIN

DOUT

Low 8 Bits (DS0–DS7) are all 0

Figure 2–6. Register 1 Write Operation Timing Diagram

2.1.6

Sigma-Delta ADC

The sigma-delta analog-to-digital converter in the device is a sigma-delta modulator with 64-

× oversampling. The

ADC provides high-resolution, low-noise performance using oversampling techniques. Due to the oversampling

employed, only single-pole antialiasing filters are required on the analog inputs.

2.1.7

Decimation Filter

The decimation filters reduce the digital data rate to the sampling rate. This is accomplished by decimating with a ratio

of 1:64. The output of the decimation filter is a 16-bit 2s-complement data word clocking at the sample rate selected

for that particular data channel. The bandwidth of the filter is 0.439

× fsample and scales linearly with the sample rate.

2.1.8

Sigma-Delta DAC

The sigma-delta digital-to-analog converter in the device is a sigma-delta modulator with 256-

× oversampling. The

DAC provides high-resolution, low-noise performance using oversampling techniques.

2.1.9

Interpolation Filter

The interpolation filter resamples the digital data at a rate of 256 times the incoming sample rate. The high-speed

data output from the interpolation filter is then used in the sigma-delta DAC. The bandwidth of the filter is 0.439

fsample and scales linearly with the sample rate.

2.1.10 Analog and Digital Loopback

The analog and digital loopbacks provide a means of testing the modem data ADC/DAC channels and can be used

for in-circuit system-level tests. The analog loopback routes the DAC low-pass filter output into the analog input where

it is then converted by the ADC into a digital word. The digital loopback, enabled by setting bit D1 in control 1 register

to 1, routes the ADC output to the DAC input on the device. Analog loopback is enabled by setting bit D3 in control

2 register to 1 (see section 6).

2.1.11 FIR Overflow Flag

The decimator FIR filter sets an overflow flag (bit D5) of control 2 register to indicate that the input analog signal has

exceeded the range of the internal decimation filter calculations. Once the FIR overflow flag has been set in the

If FIR overflow occurs, the input signal must be attenuated either by the PGA or some other method.

TLC320AD50C Datasheet(PDF) 21 Page - Texas Instruments