2–5

15

14

. . .

1

0

15

14

. . .

10

(a) 16-BIT MASTER MODE (Fsync bound)

15

17

16

. . .

1

0

17

16

. . .

1

0

17

64 SCLKs

(b) 18-BIT MASTER MODE

64 SCLKs

01

. . .

16

17

0

1

. . .

16

17

(c) 18-BIT MASTER MODE

14

. . .

10

15

14

. . .

10

15

Left

(d) 16-BIT DSP CONTINUOUS MODE

32 SCLKs

1

. . .

14

15

01

. . .

14

15

0

(e) 16-BIT DSP CONTINUOUS MODE

Mode 011

SCLK

Fsync

DOUT

LRClk

Mode 100

SCLK

Fsync

DOUT

LRClk

Mode 101

SCLK

Fsync

DOUT

LRClk

Mode 110

SCLK

Fsync

DOUT

LRClk

Mode 111

SCLK

Fsync

DOUT

LRClk

15

0

Right

Left

Right

Left

Right

Left

Right

Left

64 SCLKs

32 SCLKs

Right

Figure 2–3. Serial Master Transfer Modes

2.8.2

Slave Mode

As a slave, the TLC320AD58C receives LRClk, Fsync, and SCLK as inputs. The conversion cycle is

synchronized to the rising edge of LRClk, and the data is synchronized to the falling edge of SCLK. SCLK

must meet the setup requirements specified in the recommended operating conditions section.

Synchronization of the slave modes is accomplished with the digital power-down control.

In slave mode, Fsync is an input. Three modes are provided as shown in Figures 2–4(a) through 2–4(c).

SCLK and LRClk are externally generated and sourced. The first rising edges of SCLK and LRClk after a

power-down cycle initiate the conversion cycle. Refer to the master-mode section for signal functions.