TLC545C, TLC545I, TLC546C, TLC546I

8-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL AND 19 INPUTS

SLAS066B – DECEMBER 1985 – REVISED OCTOBER 1996

3

POST OFFICE BOX 655303

typical equivalent inputs

INPUT CIRCUIT IMPEDANCE DURING SAMPLING MODE

INPUT CIRCUIT IMPEDANCE DURING HOLD MODE

1 k

Ω TYP

Ci = 60 pF TYP

(equivalent input

capacitance)

5 M

Ω TYP

INPUT

A0 – A18

INPUT

A0 – A18

operating sequence

Access

Cycle B

(see Note C)

B0

B2

C4

twH(CS)

Don’t Care

B7

B0

B1

B2

B3

B4

B5

B6

B7

C3

C2

C1

C0

LSB

MSB

Conversion Data B

MSB

MSB

LSB

Hi-Z State

Don’t Care

MSB

LSB

(see Note B)

MSB

Previous Conversion Data A

A7

A7

A6

A5

A4

A3

A2

A1

A0

LSB

B1

B3

MSB

B4

Don’t

1

1

See Note A

tconv

Sample Cycle B

88

7

6

5

4

3

2

7

6

5

4

3

2

I/O

CLOCK

CS

DATA

OUT

ADDRESS

INPUT

Care

Access

Cycle C

Sample

Cycle C

Hi-Z

State

NOTES: A. The conversion cycle, which requires 36 system clock periods, is initiated with the eighth I/O CLOCK

↓ after CS↓ for the channel

whose address exists in memory at that time.

B. The most significant bit (MSB) will automatically be placed on the DATA OUT bus after CS is brought low. The remaining seven bits

(A6–A0) will be clocked out on the first seven I/O CLOCK falling edges.

C. To minimize errors caused by noise at the CS input, the internal circuitry waits for three system clock cycles (or less) after a chip

select transition before responding to control input signals. Therefore, no attempt should be made to clock-in address data until the

minimum chip-select setup time has elapsed.