TLC540I, TLC541I

8-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL AND 11 INPUTS

SLAS065A – OCTOBER 1983 – REVISED MARCH 1995

6

POST OFFICE BOX 655303

operating characteristics over recommended operating free-air temperature range,

PARAMETER

TEST CONDITIONS

TLC540

TLC541

UNIT

PARAMETER

TEST CONDITIONS

MIN

MAX

MIN

MAX

UNIT

EL

Linearity error

See Note 5

±0.5

±0.5

LSB

EZS

Zero–scale error

See Notes 2 and 6

±0.5

±0.5

LSB

EFS

Full-scale error

See Notes 2 and 6

±0.5

±0.5

LSB

Total unadjusted error

See Note 7

±0.5

±0.5

LSB

Self-test output code

Input A11 address = 1011,

(see Note 8)

01111101

(125)

10000011

(131)

01111101

(125)

10000011

(131)

tconv

Conversion time

See Operating Sequence

9

17

µs

Total access and conversion time

See Operating Sequence

13.3

25

µs

ta

Channel acquisition time (sample cycle)

See Operating Sequence

4

4

I/O

clock

cylces

tv

Time output data remains valid after

I/O CLOCK

↓

10

10

ns

td

Delay time, I/O CLOCK

↓ to data output

valid

300

400

ns

ten

Output enable time

See Parameter

Mt

150

150

ns

tdis

Output disable time

Measurement

Information

150

150

ns

tr(bus)

Data bus rise time

Information

300

300

ns

tf(bus)

Data bus fall time

300

300

ns

NOTES:

2. Analog input voltages greater than that applied to REF+ convert to all “1”s (11111111) while input voltages less than that applied to

REF– convert to all “0”s (00000000). For proper operation, REF+ voltage must be at least 1 V higher than REF– voltage. Also, the

total unadjusted error may increase as this differential reference voltage falls below 4.75 V.

5. Linearity error is the maximum deviation from the best straight line through the A/D transfer characteristics.

6. Zero-scale error is the difference between 00000000 and the converted output for zero input voltage; full-scale error is the difference

between 11111111 and the converted output for full-scale input voltage.

7. Total unadjusted error is the sum of linearity, zero-scale, and full-scale errors.

8. Both the input address and the output codes are expressed in positive logic.